DS21Q55 Maxim Integrated Products, DS21Q55 Datasheet - Page 148

• Manufacturer Part Number: DS21Q55
• Description: IC TXRX QUAD T1/E1/J1 SCT 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q55

• Function: Transceiver
• Interface: E1, J1, T1
• Number Of Circuits: 4
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Includes: BERT Generator and Detector, Dual HDLC Controllers
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -

Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI/HDB3 or T1
AMI/B8ZS waveform presented at the RTIP and RRING inputs. If the jitter attenuator is placed in the
receive path (as is the case in most applications), the jitter attenuator restores the RCLK to an
approximate 50% duty cycle. If the jitter attenuator is either placed in the transmit path or is disabled, the
RCLK output can exhibit slightly shorter high cycles of the clock. This is because of the highly over-
sampled digital-clock recovery circuitry. See the Receive AC Timing Characteristics in Section
more details. When no signal is present at RTIP and RRING, a receive carrier loss (RCL) condition
occurs and the RCLK is derived from the JACLK source.
22.2.1 Receive Level Indicator and Threshold Interrupt
The DS21Q55 reports the signal strength at RTIP and RRING in 2.5dB increments through RL3–RL0
located in Information Register 2 (INFO2). This feature is helpful when trouble-shooting line-
performance problems. The DS21Q55 can initiate an interrupt whenever the input falls below a certain
level through the input-level under-threshold indicator (SR1.7). Using the RLT0–RLT4 bits of the CCR4
register, the user can set a threshold in 2.5dB increments. The SR1.7 bit is set whenever the input level at
RTIP and RRING falls below the threshold set by the value in RLT0–RLT4. The level must remain
below the programmed threshold for approximately 50ms for this bit to be set.
22.2.2 Receive G.703 Synchronization Signal (E1 Mode)
The DS21Q55 is capable of receiving a 2.048MHz square-wave synchronization clock as specified in
Section 13 of ITU G.703, October 1998. In order to use the device in this mode, set the receive
synchronization clock enable (LIC3.2) = 1.
22.2.3 Monitor Mode
Monitor applications in both E1 and T1 require various flat gain settings for the receive-side circuitry.
The DS21Q55 can be programmed to support these applications through the monitor mode control bits
MM1 and MM0 in the LIC3 register
Figure 22-1. Typical Monitor Application
T1/E1 LINE
Rm
MONITOR
PORT JACK
Rm
(Figure
PRIMARY
T1/E1 TERMINATING
DEVICE
22-1).
148 of 237
X
F
M
R
SECONDARY T1/E1
TERMINATING
DEVICE
Rt
DS2156
33.3
for