TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 10

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

13. Asynchronous Serial interface (UART2)
14. Serial Expansion Interface (SEI)
iv
12.5 Data Sampling Method........................................................................................................124
12.6 STOP Bit Length.................................................................................................................125
12.7 Parity....................................................................................................................................125
12.8 Transmit/Receive Operation................................................................................................125
12.9 Status Flag...........................................................................................................................126
13.1 Configuration ......................................................................................................................129
13.2 Control ................................................................................................................................130
13.3 Transfer Data Format...........................................................................................................133
13.4 Transfer Rate.......................................................................................................................134
13.5 Data Sampling Method........................................................................................................134
13.6 STOP Bit Length.................................................................................................................135
13.7 Parity....................................................................................................................................135
13.8 Transmit/Receive Operation................................................................................................135
13.9 Status Flag...........................................................................................................................136
14.1 Features ...............................................................................................................................139
14.2 SEI Registers ......................................................................................................................140
14.3 SEI Operation .....................................................................................................................142
14.4 SEI Pin Functions ...............................................................................................................143
14.5 SEI Transfer Formats ..........................................................................................................144
14.6 Functional Description.........................................................................................................146
14.7 Interrupt Generation ............................................................................................................147
14.8 SEI System Errors ...............................................................................................................147
12.8.1
12.8.2
12.9.1
12.9.2
12.9.3
12.9.4
12.9.5
12.9.6
13.8.1
13.8.2
13.9.1
13.9.2
13.9.3
13.9.4
13.9.5
13.9.6
14.2.1
14.2.2
14.2.3
14.3.1
14.3.2
14.4.1
14.4.2
14.4.3
14.5.1
14.5.2
14.2.1.1
Data Transmit Operation...............................................................................................................................................125
Data Receive Operation.................................................................................................................................................125
Parity Error....................................................................................................................................................................126
Framing Error................................................................................................................................................................126
Overrun Error.................................................................................................................................................................126
Receive Data Buffer Full...............................................................................................................................................127
Transmit Data Buffer Empty.........................................................................................................................................127
Transmit End Flag.........................................................................................................................................................128
Data Transmit Operation...............................................................................................................................................135
Data Receive Operation.................................................................................................................................................135
Parity Error....................................................................................................................................................................136
Framing Error................................................................................................................................................................136
Overrun Error.................................................................................................................................................................136
Receive Data Buffer Full...............................................................................................................................................137
Transmit Data Buffer Empty.........................................................................................................................................137
Transmit End Flag.........................................................................................................................................................138
SEI Control Register (SECR)........................................................................................................................................140
SEI Status Register (SESR)...........................................................................................................................................141
SEI Data Register (SEDR).............................................................................................................................................141
Controlling SEI clock polarity and phase .....................................................................................................................142
SEI data and clock timing .............................................................................................................................................142
SCLK pin ......................................................................................................................................................................143
MISO/MOSI pins ..........................................................................................................................................................143
SS pin ............................................................................................................................................................................143
CPHA (SECR register bit 2) = 0 format .......................................................................................................................144
CPHA = 1 format ..........................................................................................................................................................145
Transfer rate