TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 31

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

Example 1 :Starting STOP mode from NORMAL mode by testing a port P20.
2.2.4.1
Note 4: Do not set IDLE and TGHALT to “1” simultaneously.
Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period
Note 6: When IDLE1/2 or SLEEP1/2 mode is released, IDLE is automatically cleared to “0”.
Note 7: When IDLE0 or SLEEP0 mode is released, TGHALT is automatically cleared to “0”.
Note 8: Before setting TGHALT to “1”, be sure to stop peripherals. If peripherals are not stopped, the interrupt latch of peripherals
SSTOPH:
(STOP5 to STOP2) which are controlled by the STOP mode release control register (STOPCR).
started by setting SYSCR1<STOP> to “1”. During STOP mode, the following status is maintained.
with the SYSCR1<RELM>. Do not use any key-on wakeup input (STOP5 to STOP2) for releasing STOP
mode in edge-sensitive mode.
of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR<TBTCK>.
may be set after IDLE0 or SLEEP0 mode is released.
Note 1: The STOP mode can be released by either the STOP or key-on wakeup pins (STOP5 to STOP2). How-
Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external interrupt
(1)
STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup input
The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is
STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be selected
STOP mode
input for the STOP5 to STOP2 pins which are enabled by STOPCR. This mode is used for capacitor
backup when the main power supply is cut off and long term battery backup.
does not start but instead the warm-up sequence starts immediately. Thus, to start STOP mode in the
level-sensitive release mode, it is necessary for the program to first confirm that the STOP pin input is
low and the STOP5 to STOP2 inputs are high. The following two methods can be used for confirmation.
1. Oscillations are turned off, and all internal operations are halted.
2. The data memory, registers, the program status word and port output latches are all held in the
3. The prescaler and the divider of the timing generator are cleared to “0”.
4. The program counter holds the address 2 ahead of the instruction (e.g., [SET (SYSCR1).7]) which
In this mode, STOP mode is released by setting the STOP pin high or detecting high or low edge
Even if an instruction for starting STOP mode is executed while STOP pin input is high, STOP mode
Level-sensitive release mode (RELM = “1”)
ever, because the STOP pin is different from the key-on wakeup and can not inhibit the release input,
the STOP pin must be used for releasing STOP mode.
pin signal, interrupt latches may be set to “1” and interrupts may be accepted immediately after STOP
mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before enabling in-
terrupts after STOP mode is released, clear unnecessary interrupt latches.
1. Testing a port.
2. Using an external interrupt input INT5 (INT5 is a falling edge-sensitive input).
status in effect before STOP mode was entered.
started STOP mode.
LD
TEST
JRS
DI
SET
(SYSCR1), 01010000B
(P2PRD). 0
F, SSTOPH
(SYSCR1). 7
Page 17
; Sets up the level-sensitive release mode
; Wait until the STOP pin input goes low level
; IMF ← 0
; Starts STOP mode
TMP86FH92DMG