TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 171

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

15.5.8
15.5.9
15.5.10
the ACK is complete, a serial bus interface interrupt request (INTSBI) is generated.
time that the PIN is “0”, the SCL pin is pulled-down to low level.
the software.
pins in a high level, and then, write “10” to SBIM. And switch a port mode after confirming that a bus is free.
mented in order to guarantee the contents of transferred data.
on a bus. Master 1 and Master 2 output the same data until point “a”. After that, when Master 1 outputs “1” and
Master 2 outputs “0”, since the SDA line of a bus is wired AND, the SDA line is pulled-down to the low level
by Master 2. When the SCL line of a bus is pulled-up at point “b”, the slave device reads data on the SDA line,
that is data in Master 2. Data transmitted from Master 1 becomes invalid. The state in Master 1 is called “arbitration
lost”. A master device which loses arbitration releases the SDA pin and the SCL pin in order not to effect data
transmitted from other masters with arbitration. When more than one master sends the same data at the first word,
arbitration occurs continuously after the second word.
When a serial bus interface circuit is in the master mode and transferring a number of clocks set by the BC and
In the slave mode, the conditions of generating INTSBI interrupt request are follows:
When a serial bus interface interrupt request occurs, the PIN (Bit4 in SBISRB) is cleared to “0”. During the
Either writing data to SBIDBR or reading data from the SBIDBR sets the PIN to “1”.
The time from the PIN being set to “1” until the SCL pin is released takes t
Although the PIN (Bit4 in SBICRB) can be set to “1” by the software, the PIN can not be cleared to “0” by
The SBIM (Bit3 and 2 in SBICRB) is used to set I
Set the SBIM to “10” in order to set I
Since more than one master device can exist simultaneously on a bus, a bus arbitration procedure is imple-
Data on the SDA line is used for bus arbitration of the I
The following shows an example of a bus arbitration procedure when two master devices exist simultaneously
Interrupt service request and cancel
Setting of I
Note:When the arbitration lost occurs, if the slave address sent from the other master devices is not match,
Arbitration lost detection monitor
・ At the end of acknowledge signal when the received slave address matches to the value set by the
・ At the end of acknowledge signal when a “GENERAL CALL” is received
・ At the end of transferring or receiving after matching of slave address or receiving of “GENERAL
I2CAR
CALL”
the INTSBI interrupt request is generated. But the PIN is not cleared.
2
C bus mode
2
C bus mode. Before setting of I
Page 157
2
C bus mode.
2
C bus.
2
C bus mode, confirm serial bus interface
LOW
.
TMP86FH92DMG