TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 47

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

2.4
Internal Reset Detection Flag Register
IRSTSR
(0019H)
detection flag register (IRSCR). IRSCR<SYSRSF> corresponds to system clock reset, IRSCR<ADTRF> to address
trap reset, IRSCR<WDTF> to watchdog timer reset, and IRSCR<CLKSF> to clock stop detection reset. Each of these
bits is set to “1” when the corresponding reset is generated.
(external reset) to “L” level
Internal Reset Detection Flags
After an internal reset is released, the cause of this internal reset can be identified by reading the internal reset
To clear IRSCR<SYSRSF, ADTRF, WDTF, CLKSF> to “0”, write “1” in IRSCR<FCLR> or set the RESET pin
RFCLR
7
6
-
LVD2RF
LVD1RF
TRMRF
RFCLR
SYSRF
ADTRF
WDTF
TRMRF
5
Trimming data reset de-
tection flag
Voltage detection2 reset
flag
Voltage detection1 reset
flag
System clock reset de-
tection flag
Watchdog timer reset
flag
Address latch reset de-
tection flag
Reset flag of initialized
LVD2RF
4
LVD1RF
3
Page 33
0: Initial state
1: Internal request reset flag to “0”
0: Initial state
1:Triming data reset detection flag
0: Initial state
1: Voltage detection2 reset detected
0: Initial state
1: Voltage detection1 reset detected
0: Initial state
1: System clock reset detected
0: Initial state
1: Watch dog reset detected
0: Initial state
1: Address trap reset detected
SYSRF
2
WDTF
1
ADTRF
0
(Initial value: 0*00 0000)
TMP86FH92DMG
Read
write
only
only