TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 89

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

8.2.5
Clock
Binary counter
Overflow
INTWDT interrupt request
(WDTCR1<WDTOUT>= "0")
Internal reset
(WDTCR1<WDTOUT>= "1")
request is generated. When a watchdog timer reset request is generated, the internal hardware is reset. The reset
time is maximum 24/fc [s] (1.5 μs @ fc = 16.0 MHz).
Watchdog Timer Reset
When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, a watchdog timer reset
Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-
frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have
inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an
approximate value because it has slight errors.
1
Figure 8-2 Watchdog Timer Interrupt
Write 4E
2
H
to WDTCR2
3
2
17
/fc
0
Page 75
1
2
19
/fc [s]
2
3
A reset occurs
TMP86FH92DMG
0
(WDTT=11)