TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 150

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

13.9
Status Flag
13.9
13.9.1
13.9.2
13.9.3
Status Flag
UART2SR<PERR> is set to “1”. The UART2SR<PERR> is cleared to “0” when the RD2BUF is read after
reading the UART2SR.
The UART2SR<FERR> is cleared to “0” when the RD2BUF is read after reading the UART2SR.
UART2SR<OERR> is set to “1”. In this case, the receive data is discarded; data in RD2BUF are not affected.
The UART2SR<OERR> is cleared to “0” when the RD2BUF is read after reading the UART2SR.
When parity determined using the receive data bits differs from the received parity bit, the parity error flag
When “0” is sampled as the stop bit in the receive data, framing error flag UART2SR<FERR> is set to “1”.
When all bits in the next data are received while unread data are still in RD2BUF, overrun error flag
RXD2 pin
UART2SR<FERR>
INTRXD2 interrupt
Shift register
Parity Error
Framing Error
Overrun Error
Shift register
RXD2 pin
UART2SR<PERR>
INTRXD2 interrupt
Figure 13-6 Generation of Framing Error
Figure 13-5 Generation of Parity Error
xxxx0 **
xxx0 **
Final bit
Parity
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pxxxx0
xxxx0
Stop
*
*
Stop
1pxxxx0
0xxxx0
After reading UART2SR then
RD2BUF clears FERR.
After reading UART2SR then
RD2BUF clears PERR.
TMP86FH92DMG