TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 176

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

15.6
Data Transfer of I
Note:In the slave mode, if the slave address set in I2CAR is "00H", a START Byte "01H" in I
Table 15-4 Operation in the Slave Mode
2
C Bus
TRX
1
0
the device detects slave address match and the TRX is set to "1".
INTSBI interrupt request occurs when word data transfer terminates after losing arbitration. The behavior of
INTSBI interrupt request and PIN after losing arbitration are shown in Table 15-3.
to low level. Either reading or writing from or to the SBIDBR or setting the PIN to “1” releases the SCL pin
after taking t
the AD0 (Bit1 in the SBISRB) and implements processes according to conditions listed in "Table 15-4 Op-
eration in the Slave Mode".
Table 15-3 The Behavior of INTSBI interrupt request and PIN after Losing Arbitration
INTSBI in-
terrupt re-
A serial bus interface circuit changes to a slave mode if arbitration is lost in the master mode. And an
When an INTSBI interrupt request occurs, the PIN (bit 4 in the SBICRB) is reset, and the SCL pin is set
Check the AL (Bit3 in the SBISRB), the TRX (Bit6 in the SBISRB), the AAS (Bit2 in the SBISRB), and
quest
PIN
AL
1
0
1
0
When the Arbitration Lost Occurs during Trans-
mission of Slave Address as a Master
When the slave address matches the value set by
I2CAR, the PIN is cleared to "0" by generating of
INTSBI interrupt request. When the slave address
doesn't match the value set by I2CAR, the PIN
keeps "1".
LOW
AAS
1
1
0
1
0
1
0
.
AD0
1/0
1/0
1/0
0
0
0
0
INTSBI interrupt request is generated at the termination of word data.
A serial bus interface circuit loses arbitra-
tion when transmitting a slave address. And
receives a slave address of which the value
of the direction bit sent from another master
is "1".
In the slave receiver mode, a serial bus in-
terface circuit receives a slave address of
which the value of the direction bit sent from
the master is "1".
In the slave transmitter mode, 1-word data
is transmitted.
A serial bus interface circuit loses arbitra-
tion when transmitting a slave address. And
receives a slave address of which the value
of the direction bit sent from another master
is "0" or receives a "GENERAL CALL".
A serial bus interface circuit loses arbitra-
tion when transmitting a slave address or
data. And terminates transferring word da-
ta.
In the slave receiver mode, a serial bus in-
terface circuit receives a slave address of
which the value of the direction bit sent from
the master is "0" or receives "GENERAL
CALL".
In the slave receiver mode, a serial bus in-
terface circuit terminates receiving of 1-
word data.
Conditions
Page 162
When the Arbitration Lost Occurs during Trans-
mission of Data as a Master Transmit Mode
PIN keeps "1" (PIN is not cleared to "0").
Set the number of bits in 1 word to the BC
and write transmitted data to the SBIDBR.
Test the LRB. If the LRB is set to "1", set the
PIN to "1" since the receiver does not re-
quest next data. Then, clear the TRX to "0"
to release the bus. If the LRB is set to "0",
set the number of bits in 1 word to the BC
and write transmitted data to the SBIDBR
since the receiver requests next data.
Read the SBIDBR for setting the PIN to
"1" (Reading dummy data) or write "1" to the
PIN.
A serial bus interface circuit is changed to
slave mode. To clear AL to "0", read the
SBIDBR or write the data to SBIDBR.
Read the SBIDBR for setting the PIN to
"1" (Reading dummy data) or write "1" to the
PIN.
Set the number of bits in 1-word to the BC
and read received data from the SBIDBR.
2
C bus standard is received,
Process
TMP86FH92DMG