TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 157

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

14.4
14.4.1
14.4.2
14.4.3
depends on the SEI device’s mode (master or slave). The SCLK pin, MOSI pin and MISO pin of all SEI devices are
connected with the same name pin to each other.
The TMP86FH92DMG have four input/output pins associated with SEI transfer. The functionality of each pin
SEI Pin Functions
slave.
transfer, eight serial clock pulses are output from the SCLK pin only during transfer.
from the master.
is sampled at the opposite edge where the data is stable. The active edge is determined by SEI transfer protocols.
and slave are shown in the table below.
(In case P0 Port, Input/output Control Register is P0OUTCR).
enabled). To set the MISO pin of an inactive slave device to a high-impedance state, clear the SECR<SEE> bit
to 0.
is high, the slave device ignores the serial clock from the master. Nor does it receive data from the MISO pin.
When the slave’s SS pin is L, the SEI operates as slave.
goes low, output is immediately disabled on the SCLK and MOSI pins if these pins are configured as open-drain
outputs. This causes the SESR<MODF> flag of the master device to be set. This state is called a mode fault. The
mode fault function is provided to prevent damage caused by a collision between drivers that may occur, for
example, when another device on the same bus becomes the master.
The SCLK pin functions as an output pin when SEI is set for master, or as an input pin when SEI is set for
When SEI is set for master, serial clock is output from the SCLK pin to external devices. After the master starts
When SEI is set for slave, the SCLK pin functions as an input pin.
During data transfer between master and slave, device operation is synchronized by the serial clock output
When the SS pin of the slave device is “H”, data is not taken in regardless of whether the serial clock is available.
For both master and slave devices, data is shifted in and out at a rising or falling edge of the serial clock, and
The MISO and MOSI pins are used for serial data transmission/reception. The status of each pin during master
Also, the SCLK, MOSI, and MISO pins can be set for open-drain by the each pin’s input/output control register
The MISO pin of a slave device becomes an output when the SECR<SEE> bit is set to 1 (SEI operation
The SS pin function differently when the SEI is the master and when it is a slave.
・When the SEI is a slave, this pin is used to enable the SEI transmission/reception. When the slave’s SS pin
・When the SEI is the master, the SS pin is used for SEI error input. When the SS pin of the master device
SCLK pin
MISO/MOSI pins
SS pin
Note:Noise in a slave device’s SCLK input may cause the device to operate erratically.
Table 14-3 MISO/MOSI Pin Status
Master
Slave
Page 143
Output
MISO
Input
Output
MOSI
Input
TMP86FH92DMG