TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 91

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

8.3.4
be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the SFR area,
address trap reset will be generated.
fc [s] (1.5 μs @ fc = 16.0 MHz).
Address Trap Reset
While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an attempt
When an address trap reset request is generated, the internal hardware is reset. The reset time is maximum 24/
Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-
frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have
inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an
approximate value because it has slight errors.
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TMP86FH92DMG