TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 70

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

5.3
P2 (P22 to P20) Port
5.3
low-frequency resonator connecting pin. When using this port as a port input or function pin, set the output latch to
1. The output latch is initialized to 1 when reset. When operating in dual-clock mode, connect a low-frequency reso-
nator (32.768 kHz) to the P21 (XTIN) and P22 (XTOUT) pins. When operating in single-clock mode, the P21 and
P22 pins can be used as ordinary input/output ports. We recommend using the P20 pin for external interrupt input or
STOP mode release signal input or as a port input. (When used as a port output, the interrupt latch is set by a falling
edge.)
inspect the pin status, read the P2PRD register. When the P2DR or P2PRD read instruction is executed for the P2 port,
the values read from bits 7 to 3 are indeterminate.
P2 (P22 to P20) Port
The P2 port is a 3-bit input/output port shared with external interrupt input, STOP mode release signal input, and
The P2 port has independent data input registers. To inspect the output latch status, read the P2DR register. To
The P20 port has programmable internal Pull-up resistance to be controlled by P2PUCR.
Data input (P20PRD)
Data input (P21PRD)
Data input (P22PRD)
Data output (P20)
Data output (P21)
Data output (P22)
Data input (P20)
Data input (P21)
Data input (P22)
P2PUCR<0>
Control input
OUTEN
STOP
XTEN
fs
Output latch
Output latch
Output latch
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
Figure 5-4 P2 Port
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Osc.enable
VDD
P20 (INT5, STOP)
P21 (XTIN)
P22 (XTOUT)
TMP86FH92DMG