TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 44

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

2.3
Reset Circuit
2.3
2.3.1
watchdog timer reset and a system clock reset, voltage detect reset 1,voltage detection 2,power on reset, trimming
data reset.Of these reset, the address trap reset, the watchdog timer and the system clock reset, voltage detect reset
1,voltage detection 2 are a malfunction reset. When the malfunction reset request is detected, reset occurs during the
maximum 24/fc[s].
causes the device to enter a reset state. After the power-on warming-up time (tPOWUP) has elapsed, the reset is
released. For details, refer to the section on the power-on reset circuit.
Reset Circuit
The TMP86FH92DMG has types of reset generation procedures: An external reset input, an address trap reset, a
The power-on reset signal and trimming data reset signal are input to the power-on warming-up reset circuit, which
Table 2-3 shows on-chip hardware initialization by reset action.
Table 2-3 On-chip hardware Initialization by Reset Action
Program counter
Stack pointer
General-purpose registers
(W, A, B, C, D, E, H, L, IX, IY)
Jump status flag
Zero flag
Carry flag
Half carry flag
Sign flag
Overflow flag
Interrupt master enable flag
Interrupt individual enable flags
Interrupt latches
within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized.
vector address stored at addresses FFFEH to FFFFH.
External Reset Input
The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor.
When the RESET pin is held at “L” level for at least 3 machine cycles (12/fc [s]) with the power supply voltage
When the RESET pin input goes high, the reset operation is released and the program execution starts at the
On-chip Hardware
(IMF)
(PC)
(SP)
(CF)
(HF)
(SF)
(VF)
(EF)
(ZF)
(JF)
(IL)
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
Initial Value
(FFFEH)
0
0
0
Page 30
Prescaler and divider of timing generator
Watchdog timer
voltage detection circuit
Output latches of I/O ports
Control registers
RAM
On-chip Hardware
Refer to I/O port circuitry
Refer to each of control
register
Not initialized
Initial Value
Disable
Enable
TMP86FH92DMG
0