TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 93

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

9. Time Base Timer (TBT)
9.1
9.1.1
9.1.2
Time Base Timer Control Register
timer interrupt (INTTBT).
(0036H)
TBTCR
Time Base Timer
The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base
Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; Don't care
Configuration
Control
Time Base Timer is controlled by Time Base Timer control register (TBTCR).
TBTEN
TBTCK
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
(DVOEN)
fc/2
23
21
16
14
13
12
11
or fs/2
or fs/2
9
7
or fs/2
or fs/2
or fs/2
or fs/2
or fs/2
or fs/2
Time Base Timer
enable / disable
Time Base Timer interrupt
Frequency select : [Hz]
15
13
8
6
5
4
3
TBTCK
6
Time base timer control register
(DVOCK)
Figure 9-1 Time Base Timer configuration
MPX
3
5
TBTCR
Source clock
(DV7CK)
4
0: Disable
1: Enable
TBTEN
000
001
010
011
100
101
110
111
TBTEN
Page 79
Falling edge
3
detector
DV7CK = 0
NORMAL1/2, IDLE1/2 Mode
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
2
23
21
16
14
13
12
11
9
TBTCK
1
DV7CK = 1
fs/2
fs/2
fs/2
fs/2
fs/2
fs/2
fs/2
fs/2
0
15
13
8
6
5
4
3
(Initial Value: 0000 0000)
release request
INTTBT
interrupt request
IDLE0, SLEEP0
TMP86FH92DMG
SLEEP1/2
SLOW1/2
Mode
fs/2
fs/2
-
-
-
-
-
-
15
13
R/W