TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 38
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TMP86xy92DMG
Manufacturer Part Number
TMP86xy92DMG
Description
Manufacturer
Toshiba
Datasheet
1.TMP86XY92DMG.pdf
(248 pages)
Specifications of TMP86xy92DMG
Package
SSOP30
Rom Types (m=mask,p=otp,f=flash)
M/F
Rom Size
16
Ram Size
512
Driver Led
8
Driver Lcd
-
Spi/sio Channels
1
Uart/sio Channels
2
I2c/sio Channels
1
High-speed Serial Output
-
Adc 8-bit Channels
-
Adc 10-bit Channels
6
Da Converter Channels
-
Timer Counter 18-bit Channel
-
Timer Counter 16-bit Channel
1
Timer Counter 8-bit Channel
2
Motor Channels
-
Watchdog Timer
Y
Dual Clock
Y
Clock Gear
-
Number Of I/o Ports
24
Power Supply (v)
4 to 5.5
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2.2
System Clock Controller
2.2.4.3
timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes.
IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base
IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)
Note:Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) peripherals.
1. Timing generator stops feeding clock to peripherals except TBT.
2. The data memory, CPU registers, program status word and port output latches are all held in the
3. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and
status in effect before IDLE0 and SLEEP0 modes were entered.
SLEEP0 modes.
(Normal release mode)
Figure 2-12 IDLE0 and SLEEP0 Modes
No
No
No
No
CPU and WDT are halted
Execution of the instruction
Page 24
which follows the IDLE0,
Starting IDLE0, SLEEP0
Stopping peripherals
Interrupt processing
SLEEP0 modes start
modes by instruction
TBTCR<TBTEN>
by instruction
TBT interrupt
source clock
Reset input
IMF = "1"
instruction
enable
falling
= "1"
edge
TBT
Yes
Yes
No
Yes
Yes (Interrupt release mode)
Yes
Reset
TMP86FH92DMG
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