TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 160

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

14.6
Functional Description
14.6
from its MISO pin to the master device’s MISO pin. This means that data are exchanged between master and slave
via full-duplex communication, with data output and input operations synchronized by the same clock signal. After
end of transfer, the transmit byte in 8 bit shift register is replaced with the receive byte.
transfer can be programmed to be open-drain outputs. This feature enables these pins to be connected with multiple
devices. (We recommend using these pins in open-drain output mode.)
SEI device is set as the master and all the other SEI devices on the SEI bus are set as slaves. The master device sends
data from its SCLK and MOSI pins to the SCLK and MOSI pins of a slave device.
Figure 14-4 shows how the SEI master and slave are connected.
When the master device sends data from its MOSI pin to a slave device’s MOSI pin, the slave device returns data
Figure 14-5 shows an example of how an SEI system can be configured. The general-purpose pins used for SEI
In this example, all the SCLK pins are interconnected, and all the MOSI and MISO pins are interconnected. One
The slave device selected by the master sends data from its MISO pin to the MISO pin of the master device.
Port0 Port1
Functional Description
Figure 14-5 Example of SEI System Configuration (1 Master, 2 Slaves)
SEI clock
VDD
SS SCLK MOSI MISO
Master
8-bit shift register
Master
Figure 14-4 Master and Slave Connection in SEI
MOSI
MISO
SCLK
SS
SS SCLK MOSI MISO
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5 V
Slave 0
0V
MOSI
MISO
SCLK
SS
SS SCLK MOSI MISO
8-bit shift register
Slave 1
Slave
TMP86FH92DMG