TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 39

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

(1)
(2)
Note:IDLE0 and SLEEP0 mode s start/release without reference to TBTCR<TBTEN> setting.
TBTCR<TBTCK>. After the falling edge is detected, the program operation is resumed from the in-
struction following the IDLE0 and SLEEP0 mode s start instruction. Before starting the IDLE0 or
SLEEP0 mode, when the TBTCR<TBTEN> is set to “1”, INTTBT interrupt latch is set to “1”.
TBTCR<TBTCK> and INTTBT interrupt processing is started.
・ Start the IDLE0 and SLEEP0 mode s
・ Release the IDLE0 and SLEEP0 mode s
Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed by the asynchronous
Note 2: When a watchdog timer interrupt is generated immediately before IDLE0/SLEEP0 mode is started,
IDLE0 and SLEEP0 mode s are released by the source clock falling edge, which is setting by the
IDLE0 and SLEEP0 mode s are released by the source clock falling edge, which is setting by the
Interrupt release mode (IMF・EF7・TBTCR<TBTEN> = “1”)
Normal release mode (IMF・EF7・TBTCR<TBTEN> = “0”)
TBT and TBTCR<TBTEN>.
to “0” and the operation mode is returned to the mode preceding IDLE0 and SLEEP0 mode s.
Before starting the IDLE0 or SLEEP0 mode, when the TBTCR<TBTEN> is set to “1”, INTTBT
interrupt latch is set to “1”.
releasing reset, the operation mode is started from NORMAL1 mode.
Stop (Disable) peripherals such as a timer counter.
To start IDLE0 and SLEEP0 mode s, set SYSCR2<TGHALT> to “1”.
IDLE0 and SLEEP0 mode s include a normal release mode and an interrupt release mode.
These modes are selected by interrupt master flag (IMF), the individual interrupt enable flag of
After releasing IDLE0 and SLEEP0 mode s, the SYSCR2<TGHALT> is automatically cleared
IDLE0 and SLEEP0 mode s can also be released by inputting low level on the RESET pin. After
internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period setting by
TBTCR<TBTCK>.
the watchdog timer interrupt will be processed but IDLE0/SLEEP0 mode will not be started.
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TMP86FH92DMG