TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 163

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

15. Serial Bus Interface(I
15.1
15.2
15.3
of these pins to "1". When not used as serial bus interface pins, the port is used as a normal I/O port.
noise, etc.
canceller
Noise
Note 1: The serial bus interface can be used only in NORMAL1/2 and IDLE1/2 mode. It can not be used in IDLE0, SLOW1/2
Note 2: The serial bus interface can be used only in the Standard mode of I
Note 3: Please refer to the I/O port section about the detail of setting port.
The TMP86FH92DMG has a serial bus interface which employs an I
The serial interface is connected to an external devices through SDA and SCL.
The serial bus interface pins are also used as the port. When used as serial bus interface pins, set the output latches
The following registers are used for control the serial bus interface and monitor the operation status.
A serial bus interface circuit has a software reset function, when a serial bus interface circuit is locked by an external
To reset the serial bus interface circuit, write “10”, “01” into the SWRST (Bit1, 0 in SBICRB).
And a status of software reset can be read from SWRMON (Bit0 in SBISRA).
fc/4
Configuration
Control
Software Reset
SBI control register B/
SBI status register B
・ Serial bus interface control register A (SBICRA)
・ Serial bus interface control register B (SBICRB)
・ Serial bus interface data buffer register (SBIDBR)
・ I
・ Serial bus interface status register A (SBISRA)
・ Serial bus interface status register B (SBISRB)
2
and SLEEP0/1/2 mode.
can not be used.
C bus address register (I2CAR)
clock sysn.
SBICRB/
SBISRB
Divider
I
2
Control
C bus
I
address register
2
C bus
Transfer
control
I2CAR
circuit
Figure 15-1 Serial Bus Interface (SBI)
SBI data
buffer register
2
INTSBI interrupt request
C Bus) Ver.-D (SBI)
register
SBIDBR
Shift
Page 149
SBI control register A/
SBI status register A
I
2
C bus data
control
SBICRA/
SBISRA
2
C. The fast mode and the high-speed mode
2
C bus.
canceller
Noise
SCL
SDA
control
output
Input/
TMP86FH92DMG
SCL
SDA