TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 7

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

2. Operational Description
3. Interrupt Control Circuit
Precaution for Using the Emulation Chip / Difference among Products
TMP86FH92DMG
1.1 Features......................................................................................................................................1
1.2 Pin Assignment..........................................................................................................................3
1.3 Block Diagram...........................................................................................................................4
1.4 Pin Names and Functions..........................................................................................................5
2.1 CPU Core Functions .................................................................................................................7
2.2 System Clock Controller ...........................................................................................................8
2.3 Reset Circuit ...........................................................................................................................30
2.4 Internal Reset Detection Flags.................................................................................................33
3.1 Interrupt latches (IL21 to IL2) ................................................................................................36
3.2 Interrupt enable register (EIR) ................................................................................................36
3.3
2.1.1
2.1.2
2.1.3
2.2.1
2.2.2
2.2.3
2.2.4
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
3.2.1
3.2.2
3.3.1
2.2.2.1
2.2.2.2
2.2.3.1
2.2.3.2
2.2.3.3
2.2.3.4
2.2.4.1
2.2.4.2
2.2.4.3
2.2.4.4
Interrupt Sequence .................................................................................................................38
Memory Address Map ........................................................................................................................................................7
Program Memory (Flash) ....................................................................................................................................................7
Data Memory (RAM) .........................................................................................................................................................7
Clock Generator ..................................................................................................................................................................8
Timing Generator ................................................................................................................................................................9
Operation Mode Control Circuit .......................................................................................................................................11
Operating Mode Control ...................................................................................................................................................16
External Reset Input ..........................................................................................................................................................30
Address trap reset ..............................................................................................................................................................31
Watchdog timer reset ........................................................................................................................................................31
System clock reset ............................................................................................................................................................31
Power-on Reset..................................................................................................................................................................32
Voltage detection reset.......................................................................................................................................................32
Trimming data reset...........................................................................................................................................................32
Interrupt master enable flag (IMF) ...................................................................................................................................36
Individual interrupt enable flags (EF21 to EF4) ...............................................................................................................37
Interrupt acceptance processing is packaged as follows. ..................................................................................................38
Configuration of timing generator
Machine cycle
Single-clock mode
Dual-clock mode
STOP mode
Operating Mode Transition
STOP mode
IDLE1/2 mode and SLEEP1/2 mode
IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)
SLOW mode
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