TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 158

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

14.5
SEI Transfer Formats
14.5
14.5.1
be selected between two.
The transfer formats are set using CPHA and CPOL (SECR<CPHA,CPOL>). CPHA allows transfer protocols to
SEI Transfer Formats
Figure 14-2 shows a transfer format when CPHA = 0.
Table 14-4 Transfer Format Details when CPHA = 0
CPHA (SECR register bit 2) = 0 format
Note:In slave mode, be careful not to write data while the SEF flag is set and the SS pin remains “L”.
・ In master mode, transfer is initiated by writing new data to the SEDR register. At this time, the new
・ In slave mode, writing data to the SEDR register is inhibited when the SS pin is “L”. A write during
CPOL = 0
CPOL = 1
SCLK Cycle
SCLK
(CPOL = 0)
SCLK
(CPOL = 1)
MOSI
MISO
SS
SEF
data changes state on the MOSI pin a half clock period before the shift clock starts pulsing. Use BOS
(SECR<BOS>) to select whether the data should be shifted out beginning with the MSB or LSB. The
SEF flag (SESR<SEF>) is set after the last shift cycle.
this period causes collision of writes, so that the WCOL flag (SESR<WCOL>) is set. Therefore, when
writing data to the SEDR (SEI Data Register) after the SEF flag is set upon completion of transfer,
make sure the SS pin goes “H” again before writing the next data to the SEDR register.
Internal
shift clock
Figure 14-2 Transfer Format When CPHA = 0
Communicating (IDLE)
SCLK Level when not
“H” level
“L” level
1
2
Falling edge of transfer clock
Rising edge of transfer clock
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3
Data Shift
4
5
6
Rising edge of transfer clock
Falling edge of transfer clock
7
Data Sampling
8
TMP86FH92DMG