TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 119

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

Example :Setting the timer mode with source clock fc/2
11.3
11.3.1
Table 11-4 Source Clock for Timer Counter 3, 4 (Internal Clock)
bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a 16-
bit timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up counter,
16-bit pulse width modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes.
DV7CK = 0
fc/2
The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8-
NORMAL1/2, IDLE1/2 mode
Note:In the timer mode, do not select a source clock other than those shown above.
(TimerCounter4, fc = 16.0 MHz)
fc/2
fc/2
fc/2
Function
11
and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is cleared.
After being cleared, the up-counter restarts counting.
[Hz]
7
5
3
Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output pulses.
Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the
Note 3: j = 3, 4
In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter
8-Bit Timer Mode (TC3 and 4)
Source Clock (Note)
shift register configuration in the timer mode, the new value programmed in TTREGj is in effect immediately
after the programming. Therefore, if TTREGj is changed while the timer is running, an expected operation
may not be obtained.
DV7CK = 1
fs/2
fc/2
fc/2
fc/2
3
LD
DI
SET
EI
LD
LD
[Hz]
7
5
3
(TTREG4), 0AH
(EIRH). 7
(TC4CR), 00010000B
(TC4CR), 00011000B
SLOW1/2,
SLEEP1/2
fs/2
mode
3
-
-
-
[Hz]
7
Page 105
fc = 16 MHz
Hz and generating an interrupt 80 μs later
128 μs
500 ns
8 μs
2 μs
; Sets the timer register (80 μs ÷ 2
; Enables INTTC4 interrupt.
; Sets the operating clock to fc/2
; Starts TC4.
Resolution
fs = 32.768 kHz
244.14 μs
-
-
-
7
, and 8-bit timer mode.
7
fc = 16 MHz
/fc = 0AH).
127.5 μs
32.6 ms
2.0 ms
510 μs
Maximum Setting Time
TMP86FH92DMG
fs = 32.768 kHz
62.3 ms
-
-
-