T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 103

• Manufacturer Part Number: T8207-BAL-DT
• Description: CelXpres ATM interconnect. Dry-bagget, tape & reel .
• Manufacturer: Agere Systems, Inc.

Advance Data Sheet
September 2001
Agere Systems Inc.
14 Registers
Table 67. Cell Bus Configuration/Status (CBCFS) (0130h)
Table 68. Main Interrupt Status 2 (MIS2) (0132h)
cntrl_cell_prio
cb_usr_mode
cntl_cell_rx_fifo_ovrn
cb_arb_sel*
rx_utopia_fifo_ovrn
unit_addr*
Reserved
Reserved
tx_phy_fifo_ovrn
cb_in_fifo_ovrn
Name
cell_clp1_dis
lb_cell_lost
Reserved
Reserved
Name
Bit Pos.
15:10
4:0
8:7
(continued)
5
6
9
Bit Pos.
15:7
Type
0
1
2
3
5
6
RW
RW
RW
4
RO
RO
RO
ua*[4:0] Unit Address. These bits indicate the values at the ua*[4:0] inputs.
Type
ROL
ROL
ROL
ROL
ROL
ROL
ROL
Reset
RO
1
0
0
0
0
The inputs are active-low, so these bits will have a value of 1Fh for
device zero.
Cell Bus Arbiter Select. If this bit is ‘0,’ cell bus arbiter is selected.
Only one device on the cell bus may be configured as arbiter. All
other devices should set this bit to ‘1.’
Cell Bus User Mode. If this bit is ‘0,’ 32-user mode is selected on
the cell bus. If ‘1,’ 16-user mode is selected.
Reserved.
Control Cell Priority. If this bit is cleared to ‘0,’ then cells from the
RX PHY FIFO have the highest priority, cells from the control cell
TX FIFO have next highest, and finally, cells from the loopback
FIFO have the lowest. If this bit is set to ‘1,’ then cells from the con-
trol cell TX FIFO have the highest priority, cells from the RX PHY
FIFO have the next highest priority, and finally cells from the loop-
back FIFO have the lowest priority.
Note:
Reserved.
Reset
0
0
0
0
0
0
0
0
It is recommended that this bit be set during the powerup/
reset sequence (Section 3), if necessary. It is strongly
advised not to set this bit during data flow.
Loopback Cell Lost. This bit is set if a loopback cell is
discarded when the loopback FIFO is full. An interrupt is
generated if the corresponding enable bit is set.
Reserved.
Cell Bus Input FIFO Overrun. This bit is set if the four-
cell incoming cell bus input FIFO overflows. If this bit
becomes set, mclk may be too slow compared to the
cb_wc* input. An interrupt is generated if the correspond-
ing enable bit is set.
TX PHY FIFO Overrun. This bit is set if the 128-cell TX
PHY FIFO overflows. If this bit becomes set, bandwidth to
the SDRAM may be insufficient. An interrupt is generated
if the corresponding enable bit is set.
Cell with CLP Set to One Discarded. This bit is set if
a cell with its CLP bit set to one is discarded when the
128-cell TX PHY FIFO goes over the clp_fill_limit. An inter-
rupt is generated if the corresponding enable bit is set.
RX UTOPIA FIFO Overrun. This bit is set if the RX
UTOPIA FIFO overflows. If this bit becomes set, band-
width to the translation RAM or the cell bus may be insuffi-
cient. An interrupt is generated if the corresponding enable
bit is set.
Control Cell RX FIFO Overrun. This bit is set when the
control cell RX FIFO overflows. An interrupt is generated if
the corresponding enable bit is set.
Reserved.
Description
Description
ATM Interconnect
CelXpres T8207
103