T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 106

• Manufacturer Part Number: T8207-BAL-DT
• Description: CelXpres ATM interconnect. Dry-bagget, tape & reel .
• Manufacturer: Agere Systems, Inc.

CelXpres T8207
ATM Interconnect
14 Registers
14.3.2 UTOPIA Registers
Table 74. HEC Interrupt Status 1 (HIS1) (0302h)
Table 75. HEC Interrupt Enable 1 (HIE1) (0304h)
Table 76. HEC Interrupt Status (HIS) (0306h)
Table 77. HEC Interrupt Enable (HIE) (0308h)
Table 78. LUT Interrupt Service Request (LUTISR) (030Eh)
106
hec_err_ie[31:16]
lut_int_serv[15:0]
hec_err_ie[15:0]
hec_err[31:16]
hec_err[15:0]
Name
Name
Name
Name
Name
(continued)
Bit Pos.
Bit Pos.
Bit Pos.
Bit Pos.
Bit Pos.
15:0
15:0
15:0
15:0
15:0
Type
Type
Type
Type
Type
ROL
RW
RW
RW
RO
Reset
Reset
Reset
Reset
Reset
0
0
0
0
0
HEC Error. Each bit in this field represents one of the upper
16 PHY ports where the most significant bit is port 31 and the
least significant bit is port 16. The associated bit is set when an
HEC error is detected on the PHY port. An interrupt is gener-
ated if the corresponding enable bit is set. When a HEC error
occurs, the cell is still counted as received and is translated
and routed.
HEC Error Interrupt Enable. An interrupt is generated if this
bit and the corresponding status bit are set. The interrupt is
generated until this bit or the corresponding status bit is reset.
HEC Error. Each bit in this field represents one of the lower
16 PHY ports where the most significant bit is port 15 and the
least significant bit is port 0. The associated bit is set when an
HEC error is detected on the PHY port. An interrupt is gener-
ated if the corresponding enable bit is set. When a HEC error
occurs, the cell is still counted as received and is translated
and routed.
HEC Error Interrupt Enable. An interrupt is generated if this
bit and the corresponding status bit are set. The interrupt is
generated until this bit or the corresponding status bit is reset.
LUT Interrupt Service. Each bit in this field represents one of
16 LUT configuration/status registers. The least significant bit
represents LUT 0 configuration/status register. If the corre-
sponding bit is ‘1,’ the specific LUT configuration/status register
has interrupt status bits that need servicing.
Description
Description
Description
Description
Description
Advance Data Sheet
September 2001
Agere Systems Inc.