T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 95

• Manufacturer Part Number: T8207-BAL-DT
• Description: CelXpres ATM interconnect. Dry-bagget, tape & reel .
• Manufacturer: Agere Systems, Inc.

Advance Data Sheet
September 2001
Agere Systems Inc.
14 Registers
Table 55. Main Interrupt Enable 1 (MIE1) (0104h)
cb_rh_crc_err_ie
ctrl_cell_nack_ie
ctrl_cell_sent_ie
cb_wc_miss_ie
ctrl_cell_ack_ie
cb_rc_miss_ie
cb_fs_miss_ie
ctrl_cell_av_ie
rx_prty_err_ie
cb_grnt_to_ie
BIP8_err_ie
soc_err_ie
Reserved
Name
(continued)
Bit Pos. Type Reset
15:12
10
11
0
1
2
3
4
5
6
7
8
9
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
0
0
0
0
0
0
0
0
0
0
0
0
0
Cell Bus Write Clock Missing Interrupt Enable. An interrupt is
generated if this bit and the corresponding status bit are set. The
interrupt is generated until this bit or the corresponding status bit is
reset.
Cell Bus Read Clock Missing Interrupt Enable. An interrupt is
generated if this bit and the corresponding status bit are set. The
interrupt is generated until this bit or the corresponding status bit is
reset.
Cell Bus Frame Synchronization Signal Missing Interrupt
Enable. An interrupt is generated if this bit and the corresponding
status bit are set. The interrupt is generated until this bit or the cor-
responding status bit is reset.
Bit Interleave Parity Error Interrupt Enable. An interrupt is gener-
ated if this bit and the corresponding status bit are set. The interrupt
is generated until this bit or the corresponding status bit is reset.
Control Cell Acknowledged Interrupt Enable. An interrupt is gen-
erated if this bit and the corresponding status bit are set. The inter-
rupt is generated until this bit or the corresponding status bit is reset.
Control Cell Not Acknowledged Interrupt Enable. An interrupt is
generated if this bit and the corresponding status bit are set. The
interrupt is generated until this bit or the corresponding status bit is
reset.
Cell Bus Grant Time-Out Interrupt Enable. An interrupt is gener-
ated if this bit and the corresponding status bit are set. The interrupt
is generated until this bit or the corresponding status bit is reset.
Control Cell Sent Interrupt Enable. An interrupt is generated if this
bit and the corresponding status bit are set. The interrupt is gener-
ated until this bit or the corresponding status bit is reset.
Control Cell Available Interrupt Enable. An interrupt is generated
if this bit and the corresponding status bit are set. The interrupt is
generated until this bit or the corresponding status bit is reset.
Cell Bus Routing Header CRC Error Interrupt Enable. An inter-
rupt is generated if this bit and the corresponding status bit are set.
The interrupt is generated until this bit or the corresponding status
bit is reset.
Receive Parity Error Interrupt Enable. An interrupt is generated if
this bit and the corresponding status bit are set. The interrupt is gen-
erated until this bit or the corresponding status bit is reset.
Start of Cell Error Interrupt Enable. An interrupt is generated if
this bit and the corresponding status bit are set. The interrupt is gen-
erated until this bit or the corresponding status bit is reset.
Reserved.
Description
ATM Interconnect
CelXpres T8207
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