T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 154

• Manufacturer Part Number: T8207-BAL-DT
• Description: CelXpres ATM interconnect. Dry-bagget, tape & reel .
• Manufacturer: Agere Systems, Inc.

CelXpres T8207
ATM Interconnect
19 Timing Requirements
The term mclkp in Tables 143, 144, 145, and 146, represents the period of mclk in ns.
Table 143. External LUT Memory Read Timing (cyc_per_acc = 2)
Table 144. External LUT Memory Read Timing (cyc_per_acc = 3)
Table 145. External LUT Memory Write Timing (cyc_per_acc = 2)
Table 146. External LUT Memory Write Timing (cyc_per_acc = 3)
154
Symbol
Symbol
Symbol
Symbol
t1
t2
t3
t4
t1
t2
t3
t4
t1
t2
t3
t4
t5
t6
t7
t1
t2
t3
t4
t5
t6
t7
tr_oe* Low to tr_d[7:0] Driven by SRAM Chip
tr_a[17:0] & tr_cs*[1:0] Valid to tr_d[7:0] Valid
tr_oe* High to tr_d[7:0] Invalid
tr_oe* High to tr_d[7:0] 3-State
tr_oe* Low to tr_d[7:0] Driven by SRAM Chip
tr_a[17:0] & tr_cs*[1:0] Valid to tr_d[7:0] Valid
tr_oe* High to tr_d[7:0] Invalid
tr_oe* High to tr_d[7:0] 3-State
tr_oe* High to tr_d[7:0] Driven
tr_a[17:0] Setup to tr_we* Falling Edge
tr_we* Low Pulse Width
tr_d[7:0] Setup to tr_we* Rising Edge
tr_d[7:0] Hold from tr_we* Rising Edge
tr_a[17:0] Hold from tr_we* Rising Edge
tr_d[7:0] 3-State to tr_oe* Low
tr_oe* High to tr_d[7:0] Driven
tr_a[17:0] Setup to tr_we* Falling Edge
tr_we* Low Pulse Width
tr_d[7:0] Setup to tr_we* Rising Edge
tr_d[7:0] Hold from tr_we* Rising Edge
tr_a[17:0] Hold from tr_we* Rising Edge
tr_d[7:0] 3-State to tr_oe* Low
Parameter
Parameter
Parameter
Parameter
(continued)
2 x mclkp – 1
mclkp – 4
mclkp – 1
mclkp – 4
2 x mclkp
mclkp
Min
Min
Min
Min
—
—
0
0
0
0
0
0
2
2
2
0
2
2
2
0
Typ
Typ
Typ
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2 x mclkp – 11
3 x mclkp – 11
3 x mclkp – 11
2 x mclkp – 11
mclkp
mclkp
Max
Max
Max
Max
Advance Data Sheet
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
September 2001
Agere Systems Inc.
Unit
Unit
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns