T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 98

• Manufacturer Part Number: T8207-BAL-DT
• Description: CelXpres ATM interconnect. Dry-bagget, tape & reel .
• Manufacturer: Agere Systems, Inc.

CelXpres T8207
ATM Interconnect
14 Registers
Table 58. Main Configuration/Control (MCFCT) (0110h)
Table 59. Main Configuration 2 (MCF2) (0112h)
98
addr_clav_en
cell_drop_en
Reserved
cntl_cell_wr
clp_fill_limit
cntl_cell_rd
cb_req_pr
Reserved
cb_rx_en
slave_en
Name
inv_crc
Name
Bit Pos. Type
(continued)
Bit Pos. Type
2:0
3
10:4
3:2
12
13
14
15
11
0
1
RW
RO
WO
RW
RW
RW
RW
RW
RW
RW
RO
Reset
0
0
Reset
0
0
0
0
0
0
0
1
0
UTOPIA Address, Cell Available, and Enable Signals. These bits
configure the number of address, cell available, and enable signals
on the UTOPIA bus as follows (see Section 9.6 on page 50):
“000” = 0 ADDR, 4 CLAV, 4 ENB
“001” = 4 ADDR, 1 CLAV, 1 ENB
“010” = 1 ADDR, 4 CLAV, 4 ENB
“011” = 4 ADDR, 2 CLAV, 2 ENB
Reserved.
Control Cell Has Been Read. Write ‘1’ to this bit after a control
cell is read from the control cell FIFO. The ‘1’ will pulse for one
clock cycle and will clear to ‘0’ automatically.
Control Cell Written in Control Cell Memory. Write ‘1’ to this bit
after a control cell is written in the control cell memory. This bit is
automatically cleared when the cell is transmitted to the cell bus.
Cell Bus Request Priority. These bits indicate the priority of stan-
dard requests sent on the cell bus as follows:
“00” = disabled, receives cells from cell bus but cannot transmit
“01” = low priority
“10” = medium priority
“11” = high priority
CLP Fill Limit. These bits indicate the TX PHY FIFO fill level at
which cells with their CLP bit set to one will be discarded.
Cell Drop Enable. If this bit is one, incoming cells with their CLP
bit set to one will be discarded when the TX PHY FIFO fill limit pro-
grammed in the clp_fill_limit bits is reached.
Invert CRC. If this bit is one, the CRC-4 in the routing header is
inverted before transmission to the cell bus. This bit is used to sim-
ulate errors.
Cell Bus Receive Enable. If this bit is ‘1,’ cells are received from
the cell bus. If ‘0,’ cells are not accepted.
Slave Enable. If this bit is ‘1,’ the T8207 is configured as a slave in
shared UTOPIA mode. The default value of this bit is ‘1.’ Clear this
bit if shared UTOPIA is not used. For shared UTOPIA, only one of
the two devices may have this bit cleared. Dynamically changing
this bit will cause cell loss. When this bit is ‘1,’ u_rxenb*[0] and
u_rxenb*[3:1] become inputs.
Reserved.
Description
Description
“100” = 2 ADDR, 2 CLAV, 2 ENB
“101” = 2 ADDR, 4 CLAV, 4 ENB
“110” = 3 ADDR, 1 CLAV, 1 ENB
“111” = 3 ADDR, 2 CLAV, 2 ENB
Advance Data Sheet
September 2001
Agere Systems Inc.