T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 133

• Manufacturer Part Number: T8207-BAL-DT
• Description: CelXpres ATM interconnect. Dry-bagget, tape & reel .
• Manufacturer: Agere Systems, Inc.

Advance Data Sheet
September 2001
Agere Systems Inc.
14 Registers
Table 118. Queue X (QX) (0440h to 04BEh)
queueX_fecn_lim_ie
queueX_clp_lim_ie
queueX_fecn_lim
queueX_fecn_en
queueX_ovrn_ie
queueX_clp_lim
queueX_clp_en
queueX_wr_en
queueX_rd_en
queueX_ovrn
queueX_emp
Reserved
Name
(continued)
Bit Pos.
7:4
10
12
14
11
13
0
1
2
3
8
9
Type
ROL
ROL
ROL
ROL
RW
RW
RW
RW
RW
RW
RW
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Queue X Read Enable. If this bit is ‘1,’ the queue is enabled
for read operations. When any configuration bits are
changed, this bit must be ‘0.’
Note: To prevent corruption of data, this bit must be cleared
Queue X Write Enable. If this bit is ‘1,’ the queue is enabled
for write operations. When any configuration bits are
changed, this bit must be ‘0.’
Note: To prevent corruption of data, this bit must be cleared
Queue X FECN Enable. If this bit is ‘1,’ the forward explicit
congestion notification (FECN) feature is enabled.
Queue X CLP Enable. If this bit is ‘1,’ the cell loss priority
(CLP) feature is enabled.
Reserved.
Queue X FECN Limit Reached. This bit is set when the
FECN limit has been reached in the queue. An interrupt is
generated if the corresponding enable bit is set.
Queue X CLP Limit Reached. This bit is set when the CLP
limit has been reached in the queue. An interrupt is gener-
ated if the corresponding enable bit is set.
Queue X Overrun. This bit is set when the queue overruns.
An interrupt is generated if the corresponding enable bit is
set.
Queue X Empty. This bit is set when the queue is empty. An
interrupt is generated if the corresponding enable bit is set.
Queue X FECN Limit Reached Interrupt Enable. An inter-
rupt is generated if this bit and the corresponding status bit
are set. The interrupt is generated until this bit or the corre-
sponding status bit is reset.
Queue X CLP Limit Reached Interrupt Enable. An inter-
rupt is generated if this bit and the corresponding status bit
are set. The interrupt is generated until this bit or the corre-
sponding status bit is reset.
Queue X Overrun Interrupt Enable. An interrupt is gener-
ated if this bit and the corresponding status bit are set. The
interrupt is generated until this bit or the corresponding sta-
tus bit is reset.
in unused queues.
in unused queues.
Description
ATM Interconnect
CelXpres T8207
133