T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 85

• Manufacturer Part Number: T8207-BAL-DT
• Description: CelXpres ATM interconnect. Dry-bagget, tape & reel .
• Manufacturer: Agere Systems, Inc.

Advance Data Sheet
September 2001
Agere Systems Inc.
14 Registers
Table 30. mclk PLL Configuration 1 (MPLLCF1) (2Bh)
Table 31. GTL+ Slew Rate Configuration (GTLSRCF) (2Eh)
Table 32. GTL+ Control (GTLCNTRL) (2Fh)
slew_rate[2:0]
Reserved
Reserved
pll_m[4:0]
pll_n[2:0]
Name
Name
GTLRPDN
GTLTPDN
Reserved
Reserved
Reserved
Reserved
Name
Bit Pos.
Bit Pos. Type
2:0
7:4
(continued)
4:0
7:5
3
Bit Pos.
4:3
7:6
0
1
2
5
Type
RW
RW
RW
RW
RW
Type
Reset
Reset
RW
RW
R
R
R
R
4h
0
0
1
0
Reset
GTL+ Slew Rate Control [2:0]. The slew rates of the GTL+ (cell bus)
output signals are controlled by these bits. The minimum slew rate
time is 0.9 ns and the maximum slew rate time is 3.8 ns.
“000” = Fastest slew rate
“001”
“010”
“011” = Nominal slew rate (on fast side)
“100” = Nominal slew rate (on slow side)
“101”
“110”
“111” = Slowest slew rate
Reserved. Program to ‘1.’
Reserved. Program to ‘0.’
PLL M Count Value. See Section 5, PLL Configuration, for informa-
tion on these bits.
PLL N Count Value. See Section 5, PLL Configuration, for informa-
tion on these bits.
1
1
1
0
1
0
Reserved. Program to ‘1.’
GTL+ Receive Powerdown. When this bit is cleared to ‘0,’ the
GTL+ receivers on the cell bus pins are powered down. Under
this condition, no cells can be received from the backplane.
When this bit is set to ‘1,’ the GTL+ receivers are powered up
and cells are received from the backplane.
GTL+ Transmit Powerdown. When this bit is cleared to ‘0,’
the GTL+ transmitters on the cell bus pins are powered down.
Under this condition, no cells can be transmitted to the back-
plane.
When this bit is set to ‘1,’ the GTL+ transmitters are powered
up and cells are transmitted to the backplane.
Reserved. Program to ‘0.’
Reserved. Program to ‘1.’
Reserved. Program to ‘0.’
Description
Description
Description
ATM Interconnect
CelXpres T8207
85