T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 132

• Manufacturer Part Number: T8207-BAL-DT
• Description: CelXpres ATM interconnect. Dry-bagget, tape & reel .
• Manufacturer: Agere Systems, Inc.

CelXpres T8207
ATM Interconnect
14 Registers
Table 114. SDRAM Interrupt Service Request 4 (SISR4) (0438h)
Table 115. SDRAM Interrupt Service Request 3 (SISR3) (043Ah)
Table 116. SDRAM Interrupt Service Request 1 (SISR1) (043Ch)
Table 117. SDRAM Interrupt Service Request 2 (SISR2) (043Eh)
132
queue_serv[63:48]
queue_serv[47:32]
queue_serv[31:16]
queue_serv[15:0]
Name
Name
Name
Name
(continued)
Bit Pos. Type
Bit Pos. Type
Bit Pos. Type
Bit Pos. Type
15:0
15:0
15:0
15:0
RO
RO
RO
RO
Reset
Reset
Reset
Reset
0
0
0
0
Queue Service [63:48]. Each bit in this field represents one of
16 queue X registers from the 64 queue X registers. The least
significant bit represents the queue 48 register. The most sig-
nificant bit represents the queue 63 register. If the correspond-
ing bit is ‘1,’ the specific queue X register has interrupt status
bits that need servicing (see Table 118).
Queue Service [47:32]. Each bit in this field represents one of
16 queue X registers from the 64 queue X registers. The least
significant bit represents the queue 32 register. The most sig-
nificant bit represents the queue 47 register. If the correspond-
ing bit is ‘1,’ the specific queue X register has interrupt status
bits that need servicing (see Table 118).
Queue Service [31:16]. Each bit in this field represents one of
16 queue X registers from the 64 queue X registers. The least
significant bit represents the queue 16 register. The most sig-
nificant bit represents the queue 31 register. If the correspond-
ing bit is ‘1,’ the specific queue X register has interrupt status
bits that need servicing (see Table 118).
Queue Service [15:0]. Each bit in this field represents one of
16 queue X registers from the 64 queue X registers. The least
significant bit represents the queue 0 register. The most signif-
icant bit represents the queue 15 register. If the corresponding
bit is ‘1,’ the specific queue X register has interrupt status bits
that need servicing (see Table 118).
Description
Description
Description
Description
Advance Data Sheet
September 2001
Agere Systems Inc.