T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 20

• Manufacturer Part Number: T8207-BAL-DT
• Description: CelXpres ATM interconnect. Dry-bagget, tape & reel .
• Manufacturer: Agere Systems, Inc.

CelXpres T8207
ATM Interconnect
3
One of the following two methods may be used to reset the T8207:
1.
2.
The device is now in the reset state, and the following start-up procedure must be executed to ensure proper oper-
ation:
1.
2.
3.
Extended memory accesses may now be performed only to the main register group.
4.
5.
6.
7.
8.
9.
The T8207 device is now out of reset state.
10. Initialize the SDRAM per the SDRAM specifications.
11. Enable the SDRAM by setting the sdram_en bit in the SDRAM control register (address 0400h).
12. Initialize the LUT to benign values (recommended).
13. Initialize the multicast memory to all ’0’ (recommended).
14. Program the three routing information registers (addresses 0200h through 0204h) and the seven PPD infor-
20
Assert the reset* pin low for at least 5 pclk periods or 100 ns, whichever is longer, and then return it high for a
hardware reset. For a powerup reset, the reset* pin should be held low for at least 5 pclk periods or 100 ns,
whichever is longer, after the power supply ramps to its operating voltage and the crystal oscillator is stable.
Write both the srst* and srst_reg* bits in the direct configuration/control register (address 28h) to ‘0,’ and leave
them at that value for at least 1 µs to perform a software reset.
After pclk (xtalin) is provided to the T8207, and the device is in the reset state:
A. Write the mclk PLL configuration 0 and 1 registers at addresses 2Ah and 2Bh.
B. Continue after the PLL has stabilized in 100 s.
Set the srst_reg* bit (to take the main registers out of reset), and program the cyc_per_acc and big_end bits in
the direct configuration/control register (address 28h).
Wait 1 s for the circuit to stabilize.
Write the desired values to the main configuration 1 register (address 0100h), the TX UTOPIA clock configura-
tion register (address 010Ch), and the RX UTOPIA clock configuration register (address 010Eh) in the
extended memory registers. These bits should not be modified at a later time without returning to the reset
state.
Program the main configuration 2 register (address 0112h) and the UTOPIA configuration register (address
0114h). These registers should not be modified at a later time without returning to the reset state.
Program the cb_arb_sel and cb_usr_mode bits in the cell bus configuration/status register (address 0130h).
Wait one clock period of the slowest clock (cell bus, UTOPIA, or pclk) for the circuit to stabilize.
Set the srst* bit in the direct configuration/control register (address 28h).
Wait three clock periods of the slowest clock (cell bus, UTOPIA, or pclk) for the circuit to stabilize.
mation registers (addresses 0206h through 0212h).
Powerup/Reset Sequence
Advance Data Sheet
September 2001
Agere Systems Inc.