T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 83

• Manufacturer Part Number: T8207-BAL-DT
• Description: CelXpres ATM interconnect. Dry-bagget, tape & reel .
• Manufacturer: Agere Systems, Inc.

Advance Data Sheet
September 2001
Agere Systems Inc.
14 Registers
Table 27. Direct Configuration/Control Register (DCCR) (28h)
cyc_per_acc
Reserved
Reserved
srst_reg*
big_end
rplc_gfc
Name
srst*
Bit Pos. Type
7:6
0
1
2
3
4
5
(continued)
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
Cycles Per Access. This bit is used to indicate the number of cycles
per read/write to the translation RAM.
‘0’ = 2 mclk cycles.
‘1’ = 3 mclk cycles.
Software Reset Main Registers. A logic level zero on this bit resets
the main registers only. The direct memory access registers (including
this one) are not affected by this reset. This bit must be ‘0’ while the
mclk PLL configuration 0 and 1 registers are being modified. Active-
low.
Software Reset. A logic level zero on this bit resets the entire device
except the direct memory registers and the main registers. This bit
must be ‘0’ while the mclk PLL configuration 0 and 1 registers are being
modified and clocks are not present. Active-low.
Reserved. This bit must be programmed to ‘1.’
Replace GFC. If this bit is ‘1’ and the device is in UNI mode, the GFC
field of incoming cells will be replaced during a VPI-VCI translation. If
this bit is ‘0’ and the device is in UNI mode, the GFC field will be left
untouched. When the device is in NNI mode or when a VPI only trans-
lation is performed, this bit has no effect.
Big Endian. If this bit is ‘0,’ register fields in the direct address space,
30h to 37h, will be in little-endian format. If ‘1,’ fields in the direct
address space, 30h to 37h, will be in big-endian format.
Reserved. These bits must be programmed to ‘0.’
Description
ATM Interconnect
CelXpres T8207
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