T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 107

• Manufacturer Part Number: T8207-BAL-DT
• Description: CelXpres ATM interconnect. Dry-bagget, tape & reel .
• Manufacturer: Agere Systems, Inc.

Advance Data Sheet
September 2001
Agere Systems Inc.
14 Registers
Table 79. LUT X Configuration/Status (LUTXCFS) (0320h to 033Eh)
The letter X in the register name represents the 16 PHY port look-up tables. The addresses of the 16 configuration/
status registers are shown below.
LUT 0 Configuration/Status
LUT 1 Configuration/Status
LUT 2 Configuration/Status
LUT 3 Configuration/Status
LUT 4 Configuration/Status
LUT 5 Configuration/Status
LUT 6 Configuration/Status
LUT 7 Configuration/Status
mis_cell_ie
Reserved
Reserved
Reserved
vpi_or_ie
vci_or_ie
mis_cell
Name
lut_en
vci_or
vpi_or
Register Name
(continued)
Bit Pos.
15:13
3:1
9:7
10
12
11
0
4
5
6
Type
ROL
ROL
ROL
RW
RW
RW
RW
RO
RO
RO
Register
Address
032Ch
032Eh
0320h
0322h
0324h
0326h
0328h
032Ah
Reset
0
0
0
0
0
0
0
0
0
0
LUT Memory Space Enable. If this bit is ‘1,’ the LUT memory
space is enabled. When this bit is ‘0,’ cells from the associated
PHY port are discarded, are not flagged as misrouted, and are
not counted as a received cell.
Note: When 16 or less PHY ports are used, each PHY port has
Reserved.
Misrouted Cell to LUT. This bit is set when a cell’s translation
record has its A and I bits equal to ‘0.’ An interrupt is generated
if the corresponding enable bit is set.
VCI Out of Range. This bit is set when an incoming cell’s VCI
is greater than the allowed range. An interrupt is generated if
the corresponding enable bit is set.
VPI Out of Range. This bit is set when one of the incoming
cell’s unmasked VPI bits is not ‘0’ and the lutX_vpi_chk bit
equals ‘1.’ An interrupt is generated if the corresponding
enable bit is set.
Reserved.
Misrouted Cell to LUT Interrupt Enable. An interrupt is gen-
erated if this bit and the corresponding status bit are set. The
interrupt is generated until this bit or the corresponding status
bit is reset.
VCI Out of Range Interrupt Enable. An interrupt is generated
if this bit and the corresponding status bit are set. The interrupt
is generated until this bit or the corresponding status bit is
reset.
VPI Out of Range Interrupt Enable. An interrupt is generated
if this bit and the corresponding status bit are set. The interrupt
is generated until this bit or the corresponding status bit is
reset.
Reserved.
LUT 10 Configuration/Status
LUT 12 Configuration/Status
LUT 13 Configuration/Status
LUT 14 Configuration/Status
LUT 15 Configuration/Status
LUT 11 Configuration/Status
LUT 8 Configuration/Status
LUT 9 Configuration/Status
its own look-up table memory space. For 16 or less PHY
ports, PHY port 0 uses LUT 0 memory space, PHY port
1 uses LUT 1 memory space, and so on. When greater
than 16 PHY ports are used, even and odd PHY ports
must share the look-up memory space. For greater than
16 PHY ports, PHY ports 0 and 1 use LUT 0 memory
space, PHY ports 2 and 3 use LUT 1 memory space,
PHY ports 4 and 5 use LUT 2 memory space, and so on.
Register Name
Description
ATM Interconnect
CelXpres T8207
Register
Address
033Ch
033Ah
033Eh
0330h
0332h
0334h
0336h
0338h
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