T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 77

• Manufacturer Part Number: T8207-BAL-DT
• Description: CelXpres ATM interconnect. Dry-bagget, tape & reel .
• Manufacturer: Agere Systems, Inc.

Advance Data Sheet
September 2001
Agere Systems Inc.
13 JTAG Test Access Port
Table 22
Boundary-Scan
Register Bit
102—103
108—123
129—146
147—148
150—157
159—163
166—168
171—178
90—101
104
105
106
107
124
125
126
127
128
149
158
164
165
169
170
179
84
85
86
87
88
89
.
Boundary-Scan Register Descriptions (continued)
DEVHIZ_N_HIGH_DRIVE
U_RXCLV1—U_RXCLV3
RDY_DTACK_N_OE
U_RXCLAV0_OE
U_RXADDR_OE
U_RXENB0_OE
U_RXADD(0:4)
TR_CONT_OE
U_RXCLK_OE
U_RXDAT(0:7)
SD_CLK_OE
RDYDTACK
SD_BS(0:1)
SD_CAS_N
SD_D(0:15)
SD_RAS_N
TR_CS(0:1)
SD_A(0:11)
TR_A(0:17)
U_RXCLV0
SD_WE_N
TR_WE_N
SD_D_OE
TR_D(0:7)
TR_OE_N
TR_D_OE
U_RXCLK
INT_IRQ
SD_CLK
SEL_N
WR_N
Name
(continued)
u_rxaddr[0:4] Bidirectional.
u_rxdata[0:7] Input.
u_rxclav[1:3] Input.
u_rxclav[0]
rdy_dtack*
sd_d[0:15]
Pin Name
sd_a[0:11]
sd_bs[0:1]
tr_cs*[0:1]
tr_a[0:17]
sd_cas*
tr_d[0:7]
wr*_ds*
sd_ras*
sd_we*
int_irq*
sd_clk
tr_we*
tr_oe*
sel*
T1
—
—
—
—
—
—
—
—
—
—
RDYDTACK is high impedance when
RDY_DTACK_N_OE = 0.
3-statable output.
Input.
Input.
INT_IRQ, SD_A(11:0), SD_BS(1:0), SD_CAS_N,
SD_RAS_N, and SD_WE_N are high impedance
when DEVHIZ_N_HIGH_DRIVE = 0.
3-statable output.
3-statable output.
3-statable output.
3-statable output.
SD_CLK is an input when SD_CLK_OE = 0.
Bidirectional.
SD_D(15:0) are inputs when SD_D_OE = 0.
Bidirectional.
3-statable output.
3-statable output.
TR_OE_N, TR_WE_N, TR_A(17:0), and
TR_CS(1:0) are high impedance when
TR_CONT_OE = 0.
3-statable output.
3-statable output.
3-statable output.
3-statable output.
TR_D(7:0) are inputs when TR_D_OE = 0.
Bidirectional.
U_RXADD(4:0) are inputs when U_RXADDR_OE
= 0.
U_RXCLV0 is an input when U_RXCLAV0_OE =
0.
Bidirectional.
U_RXCLK is an input when U_RXCLK_OE = 0.
Bidirectional.
U_RXENB(0) is an input when U_RXENB0_OE =
0.
Description
ATM Interconnect
CelXpres T8207
77