T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 44

Manufacturer Part Number

T8207-BAL-DT

Description

CelXpres ATM interconnect. Dry-bagget, tape & reel .

Manufacturer

Agere Systems, Inc.

Datasheet

1.T8207-BAL-DT.pdf (158 pages)

CelXpres T8207

Advance Data Sheet

ATM Interconnect

September 2001

UTOPIA Interface

(continued)

9.2

Outgoing UTOPIA Cell Interface

9.2.1

Outgoing PHY Mode (Cells Sent by T8207)

In PHY mode, only one enable (u_txenb*[0]) signal and one cell available (u_txclav[0]) signal are used. The

u_txenb*[0] signal is an input connected to the ATM layer’s RxEnb* signal, and the u_txclav[0] signal is an output

connected to the ATM layer’s RxClav signal. As a PHY device, the T8207 may use queue group 0 (queues 0, 1, 2,

and 3) in the SDRAM and TX UTOPIA cell buffer. The div_queue bits in the main configuration 2 register (address

0112h) may be programmed to “000” for 4 queues or “101” for 1 queue, and the port_rte[63:0] bits in the TX PHY

FIFO routing 0, 1, 2, and 3 registers (addresses 017Ch, 017Eh, 017Ah, and 0178h respectively) must be pro-

grammed to zero. If only queue 0 is used, configure and use only the queue 0 registers at addresses 0440h and

2000h through 2016h. Also, if only queue 0 is used, program the mphy_select bits and priority_select bits in the

routing information 1, 2, and 3 registers addresses 0200h, 0202h, and 0204h to the zero value of “110000.” If

queues 0, 1, 2, and 3 are used, configure and use only the queue 0, 1, 2, and 3 registers at addresses 0440h

through 0446h and 2000h through 2076h. Also, if queues 0, 1, 2, and 3 are used, only the mphy_select bits in the

routing information 1 and 2 registers (addresses 0200h and 0202h) must all be programmed to the zero value of

“110000.”

For UTOPIA level 2 functionality, the PHY address is programmed in the addr_match bits of UTOPIA configuration

programmed to any value mentioned in the register except “000.” As specified in the UTOPIA level 2 specification,

the T8207 drives the u_txclav[0] signal during the clock cycle following the one with its address on the u_txaddr

pins. The u_txclav[0] pin goes high impedance when not selected to support MPHY operation. When the

tx_utopia_hi_z bit in the main configuration 1 register (address 0100h) is cleared, the u_txsoc, u_txdata[7:0] and

u_txprty outputs go high impedance when not selected, allowing multiple PHYs to be connected on the same UTO-

PIA bus. In UTOPIA level 1, the above level 2 bits are not meaningful; therefore, the addr_clav_en bits must be

programmed to “000,” the u_txaddr pins must be grounded, and the addr_match bits cleared.

Note: If the SDRAM is bypassed, the T8207 uses only queue 0 in the TX UTOPIA cell buffer.

Note: Even though the outgoing (egress) queues are 0—3, the egress port is determined by the address match

bits in register 0114h.

Agere Systems Inc.