T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 135

• Manufacturer Part Number: T8207-BAL-DT
• Description: CelXpres ATM interconnect. Dry-bagget, tape & reel .
• Manufacturer: Agere Systems, Inc.

Advance Data Sheet
September 2001
Agere Systems Inc.
14 Registers
14.3.3.1 SDRAM Control Memory
Table 119. Queue X Definition Structure (QXDEF) (2000h to 27E0h)
base_addrX[24:9]
base_addrX[8:6]
end_addrX[24:9]
end_addrX[8:6]
fecn_fillX[24:9]
wr_pntX[24:9]
rd_pntX[24:9]
fecn_fillX[8:6]
clp_fillX[24:9]
wr_pntX[8:6]
rd_pntX[8:6]
clp_fillX[8:6]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Name
(continued)
Offset Bit Pos. Type Reset
0Ch
0Ah
0Eh
00h
02h
04h
06h
08h
10h
12h
14h
16h
15:13
15:13
15:13
15:13
15:13
15:13
12:0
15:0
12:0
15:0
12:0
12:0
15:0
12:0
15:0
12:0
15:0
15:0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
X
X
Base Address Queue X [24:9]. These bits configure the upper
16 bits of the queue’s base address offset in increments of one cell
(64 bytes).
Base Address Queue X [8:6]. These bits configure bits 6 through
8 of the queue’s base address offset in increments of one cell
(64 bytes).
Reserved.
End Address Queue X [24:9]. These bits configure the upper
16 bits of the queue’s end address offset in increments of one cell.
The total number of cells held by the queue may be calculated by
subtracting the base_addr from the end_addr and adding one to the
difference. The minimum size of any queue is four cells.
End Address Queue X [8:6]. These bits configure bits 6 through 8 of
the queue’s end address offset in increments of one cell. The total
number of cells held by the queue may be calculated by subtracting
the base_addr from the end_addr and adding one to the difference.
The minimum size of any queue is four cells.
Reserved.
Write Pointer for Queue X [24:9]. These bits must be initialized to
the base_addrX[24:9] before the queue is enabled.
Write Pointer for Queue X [8:6]. These bits must be initialized to the
base_addrX[8:6] before the queue is enabled.
Reserved.
Read Pointer for Queue X [24:9]. These bits must be initialized to
the base_addrX[24:9] before the queue is enabled.
Read Pointer for Queue X [8:6]. These bits must be initialized to the
base_addrX[8:6] before the queue is enabled.
Reserved.
FECN Fill for Queue X [24:9]. These bits with fecn_fillX[8:6] deter-
mine the queue’s fill level in cells (64 bytes) where the FECN bit is
set in outgoing cells. The FECN bit is set only when the
queueX_fecn_en bit is ‘1.’
FECN Fill for Queue X [8:6]. These bits with fecn_fillX[24:9] deter-
mine the queue’s fill level in cells (64 bytes) where the FECN bit is
set in outgoing cells. The FECN bit is set only when the
queueX_fecn_en bit is ‘1.’
Reserved.
CLP Fill for Queue X [24:9]. These bits with clp_fillX[8:6] determine
the queue’s fill level in cells (64 bytes) where incoming cells with their
CLP bit set will be discarded. The incoming cell is dropped at this fill
level only when the queueX_clp_en bit is ‘1.’
CLP Fill for Queue X [8:6]. These bits with clp_fillX[24:9] determine
the queue’s fill level in cells (64 bytes) where incoming cells with their
CLP bit set will be discarded. The incoming cell is dropped at this fill
level only when the queueX_clp_en bit is ‘1.’
Reserved.
Description
ATM Interconnect
CelXpres T8207
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