T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 73

• Manufacturer Part Number: T8207-BAL-DT
• Description: CelXpres ATM interconnect. Dry-bagget, tape & reel .
• Manufacturer: Agere Systems, Inc.

Advance Data Sheet
September 2001
Agere Systems Inc.
11 SDRAM Interface
11.6 SDRAM Throughput
The SDRAM clock frequency must be fast enough for cell transfers, to and from the SDRAM, to occur without over-
runs to the TX PHY FIFO or underruns to the TX UTOPIA cell buffer. Using the default values for ras2cas, cas2pre,
and pre2cmd, thirty-five clock cycles are required to transfer one cell (56 bytes) into or out of the SDRAM. The
assumed efficiency rate is 90%. Therefore, the number of cells per second that can be read or written into the
SDRAM is calculated using the following equation:
Cell Rate = (f
where f
The maximum UTOPIA and cell bus bandwidths must be calculated to ensure that the SDRAM clock frequency
supports these bandwidths. For example, assume that the total bandwidth on the UTOPIA bus is 64 Mbits/s and
that the cell bus clock rate is 33 MHz. The maximum number of cells per second that the cell bus can send is:
On the UTOPIA port, the total number of cells that can be sent is:
Thus, the total number of cells per second from the cell bus and to the UTOPIA bus is 2.21 Mcells per second. For
the cell rate equation above, the required SDRAM clock frequency is:
This is a worst-case example and assumes that all potential cells on the cell bus are going to this one device. The
SDRAM frequency calculation produces a lower frequency if the actual system characteristics are considered and
if the distribution of cells is controlled.
--------------------------------------------- -
16 cycles per cell
-------------------------------------------------------------------------------------- -
53 bytes per cell
2.21 Mcells per second
------------------------------------------------------------ -
33 MHz
mclk
0.9
is the frequency of the SDRAM clock.
64 Mbits/s
mclk
/35 cycles per cell x 90%)
= 2.06 Mcells per second.
8 bits per byte
* 35 cycles per cell = 86 MHz.
(continued)
= 151 Kcells per second.
ATM Interconnect
CelXpres T8207
73