T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 129

• Manufacturer Part Number: T8207-BAL-DT
• Description: CelXpres ATM interconnect. Dry-bagget, tape & reel .
• Manufacturer: Agere Systems, Inc.

Advance Data Sheet
September 2001
Agere Systems Inc.
14 Registers
Table 107. SDRAM Configuration (SCF) (0408h)
Reserved
pre2cmd
col_num
cas2pre
ref2cmd
ras2cas
cas_lat
Name
Bit Pos.
15:11
10:9
1:0
4:3
6:5
8:7
2
(continued)
Type
RW
RW
RW
RW
RW
RW
RO
Reset
2h
2h
0
0
0
1
0
Column Number. These bits are used to indicate the number of col-
umns in the SDRAM.
“100” = 256 columns
“01” = 512 columns
“10” = 1024 columns
“11” = reserved
CAS Latency. This bit is used to indicate the CAS latency of the
SDRAM based on the clock frequency and speed grade of the device.
‘0’ = 2 cycles
‘1’ = 3 cycles
RAS Inactive to CAS Active Delay. These bits specify the minimum
time in SDRAM clock cycles from RAS going inactive to CAS going
active.
“01” = reserved
“10” = 2 clock cycles
“11” = 3 clock cycles
“00” = 4 clock cycles
CAS Inactive to Precharge Active Delay. These bits specify the min-
imum time in SDRAM clock cycles from CAS going inactive to the pre-
charge command going active.
“01” = 1 clock cycles
“10” = 2 clock cycles
“11” = 3 clock cycles
“00” = 4 clock cycles
Precharge Inactive to Next Command Active Delay. These bits
specify the minimum time in SDRAM clock cycles from the precharge
command going inactive to next command going active.
“01” = 1 clock cycles
“10” = 2 clock cycles
“11” = 3 clock cycles
“00” = 4 clock cycles
CBR Refresh Inactive to Next CBR Refresh Command Active
Delay. These bits specify the minimum time in SDRAM clock cycles
from the refresh command going inactive to next refresh command
going active. The minimum time from the refresh command to any
other command is 15 clock cycles.
“00” = 15 clock cycles
“01” = reserved
“10” = 3 clock cycles
“11” = 7 clock cycles
Reserved.
Description
ATM Interconnect
CelXpres T8207
129