T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 145

• Manufacturer Part Number: T8207-BAL-DT
• Description: CelXpres ATM interconnect. Dry-bagget, tape & reel .
• Manufacturer: Agere Systems, Inc.

Advance Data Sheet
September 2001
Agere Systems Inc.
19 Timing Requirements
The following section describes the timing requirements. Capacitve loading is in the range of 10 pF to 50 pF,
unless otherwise specified.
Some timing requirements are dependent on the frequency of pclk or mclk. The terms mclkp and pclkp refer to the
period of their respective clocks in ns when used in the following tables.
Table 133. Input Clocks
Note: The cell bus write clock (cb_wc*) should be delayed 1.5 ns to 4 ns relative to the cell bus read clock (cb_rc*) to ensure sufficient data hold
Table 134. Output Clocks
Clock Name Frequency
Clock Name
cb_wc*
u_rxclk
u_txclk
u_rxclk
u_txclk
cb_rc*
sd_clk
time.
Frequency (Max)
66 MHz
50 MHz
50 MHz
66 MHz
(Max)
100 MHz
50 MHz
50 MHz
2.0 V
2.0 V
High
—
—
Voltage Level
Rise Time (Max)
1.0 ns
2.0 ns
2.0 ns
0.8 V
0.8 V
Low
—
—
Fall Time (Max)
Rise Time
4.0 ns
4.0 ns
(Max)
—
—
1.0 ns
2.0 ns
2.0 ns
Fall Time
4.0 ns
4.0 ns
(Max)
—
—
Pulse Width (Min)
High
4 ns
8 ns
8 ns
6.06 ns
6.06 ns
High
Pulse Width (Min)
8 ns
8 ns
ATM Interconnect
Low
4 ns
8 ns
8 ns
CelXpres T8207
6.06 ns
6.06 ns
Low
8 ns
8 ns
15 pF
40 pF
40 pF
Load
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