T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 105

• Manufacturer Part Number: T8207-BAL-DT
• Description: CelXpres ATM interconnect. Dry-bagget, tape & reel .
• Manufacturer: Agere Systems, Inc.

Advance Data Sheet
September 2001
Agere Systems Inc.
14 Registers
Table 70. Misrouted LUT 1 (MLUT1) (0142h)
Table 71. Misrouted LUT 2 (MLUT2) (0144h)
Table 72. Misrouted Cell Header High (MCHH) (0146h)
Table 73. Misrouted Cell Header Low (MCHL) (0148h)
mis_cell_header[31:16]
mis_cell_header[15:0]
mis_cell_lut_sel
lst_mis_cell_lut
mis_cell_latch
mis_cell_clr
Reserved
Reserved
Name
Name
Name
Name
(continued)
Bit Pos.
Bit Pos.
Bit Pos.
Bit Pos.
15:0
15:8
15:0
15:0
7:4
3:2
0
1
Type
Type
Type
Type
WO
RW
RO
RO
RO
RO
RO
RO
FFFFh Misrouted Cell LUT Select. Each bit in this field repre-
Reset
Reset
Reset
Reset
0
0
0
0
0
0
0
sents one of 16 look-up table memory spaces. The least
significant bit is LUT memory space 0. If the correspond-
ing bit is ‘1,’ misrouted cells from the LUT memory space
are monitored.
Misrouted Cell Header Clear. Write ‘1’ to this bit to clear
the previously latched misrouted cell header. The ‘1’ will
pulse for one clock cycle and will clear to ‘0’ automatically.
Misrouted Cell Header Latched. If this bit is set to ‘1,’ a
misrouted cell was detected and is stored to the
mis_cell_header bits.
Reserved.
Last Misrouted Cell LUT. These bits indicate the LUT
memory space from which the last misrouted cell was
detected.
Reserved.
Misrouted Cell Header Bits [31:16]. These bits are cell
header bits [31:16] from the first misrouted cell received
after the mis_cell_clr bit was set. A cell is considered mis-
routed if its A and I bits are “00,” if its VCI is out of range,
or if the lutX_vpi_chk bit is ‘1’ and the unused VPI bits in
the incoming cell header are not all zero.
Misrouted Cell Header Bits [15:0]. These bits are cell
header bits [15:0] from the first misrouted cell received
after the mis_cell_clr bit was set. A cell is considered mis-
routed if its A and I bits are “00,” if its VCI is out of range,
or if the lutX_vpi_chk bit is ‘1’ and the unused VPI bits in
the incoming cell header are not all zero.
Description
Description
Description
Description
ATM Interconnect
CelXpres T8207
105