AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 12

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

Freescale Semiconductor, Inc.
Overview of Target Microprocessors
2.3.2.2
MPC7400 Compiler Model
A good compiler scheduling model for the MPC7400 includes the dispatch limitations of two instructions
per clock, a base model of the CQ with maximum of eight instructions, the completion limitation of two
instructions per clock, and the execution units—SRU, IU1, IU2, FPU, VPU, VALU (VSIU, VCIU, VFPU),
and LSU with typical execution unit latencies as given in Appendix A, “MPC7450 Execution Latencies.”
A full model incorporates full table-driven latency/throughput/serialization specifications given instruction
by instruction in Appendix A, “MPC7450 Execution Latencies.” The concept of reservation stations
(especially the second LSU reservation station) should be added. The rename registers limitations are much
more important than in the MPC750, as the number of rename registers (6) do not match the number of
completion entries (8).
2.3.3
MPC7450 Microprocessor
This section provides an overview of the MPC7450. More details are available in Part III, “MPC7450
Microprocessor Details.”
Different resource sizes, the issue queues, and the splitting of completion and execution stages are the main
differences between the MPC7450 and the MPC750/MPC7400 models. Also, the MPC7450 can dispatch
up to three instructions per cycle (compared to two on the MPC7400) and can complete a maximum of three
instructions per cycle (compared to two on the MPC7400).
With the addition of extra integer units, the MPC7450 has more integer computing capacity available for
scheduling. The MPC7450 has three single-cycle IUs (IU1a, IU1b, IU1c) that execute all integer
(fixed-point) instructions (addition, subtraction, logical operations—AND, OR, shift, and rotate) except
multiply, divide, and move to/from special-purpose register instructions. Note that all IU1 instructions
execute in one cycle, except for some instructions like tw[i] and sraw[i][.], which take two. In addition, it
has one multiple-cycle IU (IU2) that executes miscellaneous instructions including the CR logical
operations, integer multiplication and division instructions, and move to/from special-purpose register
instructions. The issue requirements for the vector subunits are also improved which is described in detail
in Section 3.3.2, “Vector Issue Queue (VIQ).”
The longer pipeline of the MPC7450 is more sensitive to branch mispredictions. Taken branches of
MPC7450 cause a single-cycle fetch bubble, whereas most taken branches on the MPC750/MPC7400 were
nearly free. The MPC7450 also changes the load-use latency, which is critical to adjust to achieve best
performance on many applications. Also, serialized instructions are more costly in terms of performance on
this microprocessor.
Figure 2-5 is a functional block diagram of the MPC7450.
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MPC7450 RISC Microprocessor Family Software Optimization Guide
MOTOROLA
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