AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 44

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

Optimizations to Exploit the MPC7450 Microprocessor
Part IV
Microprocessor Application to Optimal Code
Although many of the code optimizations described in this document can also be performed by hand in
assembly language, this chapter focuses on improving the code performance on an established compiler tool
chain.
If the goal is instead to build a compiler for the PowerPC architecture, a useful (but outdated) document is
the PowerPC Compiler Writer’s Guide. However, many of the code sequences suggested in that document
are no longer optimal, especially for the MPC7450.
There are multiple locations in the compiler tool chain, independent of the source language used, in which
code can be transformed to better exploit the architecture and microarchitecture. The optimizations in this
chapter are loosely classified into expected work and benefit. The actual work depends on the compiler tool
chain infrastructure.
4.1
The MPC7450 microprocessor has more functional units and extends the basic pipeline compared with
previous microprocessors that implement the PowerPC architecture. Running code on an MPC7450 that
was targeted or optimized for a previous microprocessor may leave some functional units idle and may
cause the pipeline to stall more often. Although the MPC7450 attempts to dynamically reorder code, a
compiler can often do a much better job.
This section describes several optimizations that take advantage of features of the MPC7450 processor.
Instruction scheduling is likely to provide the largest performance impact. Also, due to the MPC7450 deeper
pipeline, some serializing instructions have a higher performance penalty than on previous processors; their
use should be carefully examined to see if an alternate instruction will suffice. Finally, because some
instruction timings have changed, some commonly used code sequences can be modified to run faster.
4.1.1
To get good performance, the compiler must schedule the code for the target microprocessor. A good first
approximation at an optimal schedule can be obtained by modeling the number of instructions that can be
issued per clock, the number and types of functional units, the pipeline stages for each type of instruction
and the number of cycles spent in each stage, as well as the overall latency of the instruction. More
sophisticated scheduling models may incorporate the issue and completion queue sizes. The details
necessary for modifying the internal scheduling models can be found in the preceding chapters.
4.1.2
There are several instructions that cause execution serialization, either always (carry consuming instructions
like adde and subfe, for example), or under certain conditions (such as overflow-recording-form
instructions that change XER[SO]). As the pipeline gets longer, the potential loss of performance due to
serialization gets higher. Care should be exercised during instruction selection to avoid those serializations
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Optimizations to Exploit the MPC7450
Microprocessor
Instruction Scheduling
Instruction Form Selection
MPC7450 RISC Microprocessor Family Software Optimization Guide
Freescale Semiconductor, Inc.
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