AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 20

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

Fetch/Branch Considerations
3.1.2
The cost of mispredictions increases with pipeline length. The following section shows common problems
and suggests how to minimize them.
3.1.2.1
Table 3-5 uses the same code as the two previous examples but assumes the bne mispredicts. The compare
executes in cycle 5, which means the branch mispredicts in cycle 6 and the fetch pipeline restarts at that
correct target for the add in cycle 7. This particular mispredict effectively costs seven cycles (add dispatches
in cycle 2 in Table 3-3 and in cycle 9 in Table 3-5).
3.1.2.2
CTR should be used whenever possible for branch loops, especially for tight inner loops. After the CTR is
loaded (using mtctr), a branch dependent on the CTR requires no directional prediction in any of the
MPC750/MPC7400 devices. Additionally, loop termination conditions are always predicted correctly,
which is not so with the normal branch predictor.
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For the example, assume the inner loop executes four times per outer iteration. On a MPC7450 and also on
MPC750/MPC7400 microprocessors, inner loop termination is always mispredicted because the branch
predictor learns to predict the inner bne as taken, which is wrong every fourth time. Table 3-6 shows that
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lwz
cmpi
bne
add
Instruction
Branch Conditionals
Branch Mispredict Example
Branch Loop Example
outer_loop: addi. r6,r6,#FFFF
inner_loop: addic. r7,r7,#FFFF
MPC7450 RISC Microprocessor Family Software Optimization Guide
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beq
add
Instruction
Table 3-4. Eliminating the Branch-Taken Bubble
Freescale Semiconductor, Inc.
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cmpi 1,r6,#0
lwzu r10,0x4(r9)
add r11,r11,r10
bne inner_loop
stwu r11,0x4(r8)
xor r11,r11,r11
ori r7,r0,#4
bne cr1,outer_loop
Table 3-5. Misprediction Example
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