AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 9

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

Instructions are fetched from the instruction cache and placed into a six-entry IQ. When the fetch pipeline
is fully utilized, as many as four instructions can be fetched to the IQ during each clock cycle, subject to
cache block wrap restrictions.
2.3.1.1
The bottom two IQ entries are available for dispatch, which involves the following operations:
2.3.1.2
An instruction in the bottom of a reservation station is available for execution. Execution involves the
following operations:
2.3.1.3
The bottom two CQ entries are available for completion, which involves the following operations:
2.3.1.4
Branches are handled differently from other instructions. Branch instructions must be executed by the
branch unit before they can be dispatched. The BPU searches the six-entry IQ for the oldest unexecuted
branch, and executes it. If the branch instruction does not update the architectural state by setting the link
or count register, it is eligible for folding. In branch execution, the instruction is folded immediately if the
branch is taken. In this case, folding removes the branch instruction from the IQ, so the branch instruction
does not reach the dispatcher. If the branch is not taken, the dispatcher must dispatch the branch. However,
the branch is not allocated in the CQ, so no completion is required either.
MOTOROLA
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Renaming—Six rename registers are available for integer operation and six more are available for
floating-point operations.
Dispatching—A reservation station must be available for the correct execution unit.
CQ check—An entry must be available in the six-entry CQ.
Branch check—A branch instruction must have executed before being dispatched. Section 2.3.1.4,
“Branches,” provides additional information.
Busy check—The unit must be available. For example, some units are not fully pipelined.
Operand check—All source operands must be available before any execution can start.
Serialization check—If the instruction is execution serialized, it must wait to become the oldest
instruction in the machine (bottom of the CQ entry) before it can start execution.
Finish check—Only instructions that have finished or are in the last stage of execution are eligible
for finishing.
Rename check—The MPC750 can write back only two rename registers per cycle. Some
instructions, such as a load-with-update, have multiple renamed targets. If a load-with-update and
an add instruction are in the bottom two CQ entries, the add cannot complete because the
load-with-update already requires two rename-register-writeback slots for the subsequent cycle.
Dispatch
Execution
Completion
Branches
In the MPC750, execution and completion can occur simultaneously for
single-cycle execution instructions.
MPC7450 RISC Microprocessor Family Software Optimization Guide
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
NOTE
Overview of Target Microprocessors
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