AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 34

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AN2203

Manufacturer Part Number
AN2203
Description
MPC7450 RISC Microprocessor Family Software Optimization Guide
Manufacturer
Freescale Semiconductor / Motorola
Datasheet

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FPU Considerations
The timing for this sequence in Table 3-17 assumes that the load misses in the data cache. Here, after the
first four fadds, the MPC7450 runs out of FPSCR rename registers and the pipeline stalls. When the load
completes, the pipeline restarts after an additional 2-cycle lag.
Note that denormalized numbers can cause problems for the FPU pipeline, so the normal latencies in
Table A-6 may not apply. Output denormalization in the very unlikely worst case can add as many as three
cycles of latency. Input denormalization takes four to six additional cycles, depending on whether one, two,
or three input source operands are denormalized.
3.6.1
On the MPC7450, the four vector execution units are fully independent and fully pipelined. Table 3-18
shows the latencies.
VFPU latency is usually four cycles, but some instructions, particularly the vector float compares and vector
float min/max (see Table A-8 to Table A-11 for a list) have only a 2-cycle latency. This can create
competition for the VFPU register forwarding bus. This is solved by forcing a partial stall when a bypass is
needed. Consider the following code example:
xxxxxx20
xxxxxx24
xxxxxx28
xxxxxx2C
xxxxxx30
Table 3-19 shows the timing for this vector compare bypass/stall situation. In cycle 6 the vcmp bypasses
from E0 to E3, stalling the vsubfp and vlogefp for a cycle in stages E1 and E2. Note that an instruction in
E1 stalls in E1 under a bypass scenario even if no instruction is in E2.
34
lfdu
fadd
fadd
fadd
fadd
fadd
fadd
fadd
fadd
Instruction
Vector Units
MPC7450 RISC Microprocessor Family Software Optimization Guide
F2
F2
F2
F2
F1
D
D
0
vaddfp v10,v11,v12
vsubfp v11,v14,v13
vaddfp v12,v13,v14
vcmpbfp. v13,v18,v19
vmaddfp v14,v20,v21,v14
F2
D
1
I
I
Table 3-18. Vector Execution Latency Summary
Freescale Semiconductor, Inc.
E0
E0
D
2
Table 3-17. FPSCR Rename Timing Example
I
For More Information On This Product,
E1
E1
E0
D
3
I
E2
E1
E0
Go to: www.freescale.com
D
4
I
VFPU
VIU1
VIU2
VPU
Unit
E3
E2
E1
E0
D
5
I
E4
E3
E2
E1
D
6
Typical Latency
E4
E3
E2
E0
F
7
I
1
4
4
2
E4
E3
E1
E0
D
8
F
I
E4
E2
E1
E0
F
9
I
E3
E2
E1
E0
10
F
11
E4
E3
E2
E1
E4
E3
E2
E1
12
C
C
C
E4
E3
E2
E1
13
C
C
E4
E3
E2
E1
14
MOTOROLA
E4
E3
E2
15
F

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