AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 15

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

The MPC7450 has two more IUs than the MPC750/MPC7400. However, the integer unit capabilities have
changed slightly from the MPC750/MPC7400 to the MPC7450, as shown in Table 2-4. Appendix A,
“MPC7450 Execution Latencies,” compares latencies between MPC750, MPC7400, and MPC7450 for
various instructions.
2.3.3.7
The bottom three CQ entries are available for retiring instructions. Completion involves the following
operations:
2.3.3.8
Branches are handled differently from other instructions. Branch instructions must be executed by the
branch unit before they can be dispatched. The BPU searches the bottom eight entries of the IQ for the oldest
unexecuted branch, and executes it. A branch instruction is eligible for folding if it does not update the
architectural state by setting the link or count register. In branch execution, the instruction is folded
immediately if the branch is taken. In this case, folding removes the branch instruction from the IQ, so the
branch instruction does not reach the dispatcher. If the branch is not taken, the dispatcher must dispatch the
branch and the branch is placed in the CQ.
If the branch is either b or bc , a taken branch can get instructions from the BTIC. The BTIC lookup is
automatically performed based on the instruction address of the executing branch, and produces instructions
starting at the branch target address. Taken branches have a minimum one-cycle fetch bubble, as the BTIC
supplies four instructions on the following cycle. Indirect branches such as bcctr or bclr do not get
instructions from the BTIC. Thus, taken branches incur a two-cycle fetch bubble when they execute. From
MOTOROLA
•
•
•
•
add, subtract, logical, shift/rotate
mul , div
mtspr , mfspr , CR logical, and other miscellaneous instructions
Operand check—All source operands must be available before any execution can start.
Serialization check—If the instruction is execution serialized, it must wait to become the oldest
instruction in the machine (bottom of the CQ entry) before it can start execution.
Finish check—Only instructions that have finished can complete (except store instructions, which
finish and complete simultaneously to allow pipelining).
Rename check—An MPC7450 can write back only three rename registers per cycle. Some
instructions, such as a load-with-update, have multiple renamed targets. If a load-with-update is
followed by two adds, only the load-with-update and the first add can complete at the same time
(although all three instructions are finished executing), as the load-with-update requires two of the
three rename-register-writeback resources. Due to this resource constraint, the second add waits
until the second cycle is completed.
Completion
Branches
Note that in the MPC750, the dispatched (fall-through) foldable branches
are not allocated in the CQ.
MPC7450 RISC Microprocessor Family Software Optimization Guide
Table 2-4. MPC750/MPC7400 vs. MPC7450 Integer Unit Breakdown
Instruction Class
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
NOTE
MPC750/MPC7400
Overview of Target Microprocessors
IU1 or IU2
SRU
IU2
IU1 (any of 3)
MPC7450
IU2
IU2
15