AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 29

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

Because the MPC7450 can dispatch only one LSU operation per cycle, the lmw is micro-oped at a rate of
one per cycle and so in this example takes seven cycles to dispatch all the operations. However, when the
last operation in the multiple is dispatched (cycle 8), instructions 1 and 2 can dispatch along with it.
The use of load/store string instructions is strongly discouraged.
3.3
Instructions cannot be issued unless the specified execution unit is available. The following sections
describe how to optimize use of the three issue queues.
3.3.1
As many as three instructions can be dispatched to the six-entry GPR issue queue (GIQ) per cycle. As many
as three instructions can be issued in any order to the LSU, IU2, and IU1 reservation stations from the
bottom three GIQ entries.
Issuing instructions out-of-order can help in a number of situations. For example, if the IU2 is busy and a
multiply is stalled at the bottom GIQ entry (unable to issue because both IU2 reservation stations are being
used), instructions in the next two GIQ entries can be issued to LSU or IU1s, bypassing that multiply.
The following sequence is not well scheduled, but effectively, the MPC7450 micro-architecture
dynamically reschedules around the potential multiply bottleneck.
0
1
2
3
4
5
6
7
Table 3-12 shows the timing for the instruction in GIQ entries. Instruction 3 issues out-of-order in cycle 2;
instructions 4 and 5 issue out-of-order in cycle 3.
Note that instruction 7 (subf) does not issue in cycle 4 because all three IU1 reservation stations have an
instruction (4, 5, and 6). Instructions 4 and 5 are waiting in the reservation station for their source registers
to be forwarded from the IU2 and LSU, respectively. Because instruction 6 executes immediately after issue
(in cycle 5), instruction 7 can issue in that cycle.
MOTOROLA
Instr.
No.
0
1
2
3
4
5
6
Issue Queue Considerations
xxxxxx00
xxxxxx04
xxxxxx08
xxxxxx0C
xxxxxx10
xxxxxx14
xxxxxx18
xxxxxx20
General Purpose Issue Queue (GIQ)
mulhw
mulhw
mulhw
lwzu
add
add
add
Instruction
MPC7450 RISC Microprocessor Family Software Optimization Guide
Freescale Semiconductor, Inc.
F2
F2
F2
—
D
D
D
0
For More Information On This Product,
mulhw r10,r20,r21
mulhw r11,r22,r23
mulhw r12,r24,r25
lwzu r13,0x4(r9)
add r10,r10,r11
add r13,r13,r25
add r14,r5,r4
subf r15,r6,r4
—
—
—
D
D
D
1
I
Table 3-12. GIQ Timing Example
Go to: www.freescale.com
E0
—
—
—
D
2
I
I
E0
E0
—
—
—
—
3
I
E1
E0
E1
—
—
4
I
I
E0
E2
—
—
—
E
5
F
E1
E0
—
—
—
C
E
6
E0
—
—
—
7
F
E
Issue Queue Considerations
E1
—
—
—
—
C
8
—
—
—
—
F
9
10
—
—
C
C
C
11
C
C
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