AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 7

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

Table 2-3 briefly explains the MPC7450 pipeline stages.
The MPC7450 pipeline is longer than the MPC750/MPC7400 pipeline, particularly in the primary load
execution part of the pipeline (3 cycles vs. 2 cycles). Better processor performance often requires designs
to operate at higher clock speeds. Clock speed is inversely related to the work performance of the processor.
Therefore, higher clock speeds imply less work to be performed per cycle, which necessitates longer
pipelines. Also, increased density of the transistors on the chip has enabled the addition of sophisticated
branch-prediction hardware, additional processor resources, and out-of-order execution capability. This
industry trend should continue for at least one more microprocessor generation.
The longer pipelines yield a processor more sensitive to code selection and ordering. As hardware can add
additional resources and out-of-order processing ability to reduce this sensitivity, the hardware and the
software must work together to achieve optimal performance.
2.3
This section provides a high level overview of the three target microprocessors, with first-order details that
are useful in developing a compiler model of the microprocessor.
2.3.1
Figure 2-3 shows a functional block diagram of the MPC750.
MOTOROLA
Fetch2
Branch execute
Dispatch
Issue
Execute
Completion
Write back
Overview of Target Microprocessors
MPC750 Microprocessor
Pipeline Stage
MPC7450 RISC Microprocessor Family Software Optimization Guide
Fetch1
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Abbreviation
E, E0, E1, ...
Table 2-3. MPC7450 Pipeline Stages
WB
BE
F1
F2
D
C
I
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First stage of reading from instruction cache
Second stage of reading from instruction cache
Execute branch and redirect fetch if needed
Decode, dispatch to IQs, assigned to rename register
Issue to execution units, register file read
Instruction execution
Instruction completion
Architectural update
Comment
Overview of Target Microprocessors
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