AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 38

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

Load/Store Unit (LSU)
3.7.5
Misalignment, particularly the back-to-back misalignment of loads, can cause negative performance effects.
The MPC7450 splits misaligned transactions into two transactions, so misaligned load latency is at least one
cycle greater than the default latency. On the MPC7450, misalignment typically occurs when an access
crosses a double-word boundary.
Table 3-24 shows what is considered misaligned based on the EA of the access. Accesses marked as
misaligned are split into two transactions and incur an extra cycle of latency. Accesses that are not marked
are considered aligned. Note that vector transactions ignore non-size-aligned low-order address bits and so
are considered aligned.
Future generations of high-performance microprocessors that implement the PowerPC architecture may
experience greater misalignment penalties.
3.7.6
The MPC7450 supports as many as five outstanding load misses in the load miss queue (LMQ). Table 3-25
shows a load followed by a dependent add. Here, the load misses in the data cache and the full line is
reloaded from the L2 cache back into the data cache. The load L2 cache hit latency is effectively nine cycles.
38
Size in Bytes
stw r3,0x0(r9)
lwz r4,0x0(r9)
EA[29–31]
Instruction
000
001
010
011
100
101
110
111
Misalignment Effects
Load Miss Pipeline
Byte
—
—
—
—
—
—
—
—
MPC7450 RISC Microprocessor Family Software Optimization Guide
1
E0
0
I
Misaligned Misaligned
Half Word
Table 3-23. Load/Store Interaction (Assuming Full Alias)
—
—
—
—
—
—
—
2
Freescale Semiconductor, Inc.
Table 3-24. Misaligned Load/Store Detection
E1
E0
For More Information On This Product,
1
Misaligned
Misaligned
Integer
—
—
—
—
—
FSQ0/C
Go to: www.freescale.com
E1
2
Multiple-Integer
(lmw/stmw)
Alignment
Alignment
Alignment
Alignment
Alignment
Alignment
exception
exception
exception
exception
exception
exception
WB0
E1
3
—
—
4
WB1
E1
4
Floating-Point
Alignment
Alignment
Alignment
Alignment
Alignment
Alignment
exception
exception
exception
exception
exception
exception
Single
CSQ0
—
—
E1
5
CSQ0
Floating-Point
E2
6
Misaligned
Alignment
Alignment
Alignment
Alignment
Alignment
Alignment
exception
exception
exception
exception
exception
exception
Double
—
8
CSQ0
C
7
MOTOROLA
Align to QW
Align to QW
Align to QW
Align to QW
Align to QW
Align to QW
Align to QW
Bus!=60x
CSQ0
16
—
8