AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 24

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

Fetch/Branch Considerations
ack:
The bl in main pushes a value onto the hardware managed link stack (in addition to the
architecturally-defined link register). Then the bl in foo pushes a second value onto the stack.
When ack later returns through the bclr, the hardware link stack is used to predict the value of the LR, if
the actual value of the LR is not available when the branch is executed (typically because the lwzu/mtlr pair
has not finished executing). It also pops a value off of the stack, leaving only the first value on the stack.
This occurs again with the bclr in foo which returns to main, and this pop leaves the stack empty.
Table 3-8 shows the performance implications of the link stack. The following code starts executing from
instruction 0 in procedure foo.
With the link stack prediction, the BPU can successfully predict the target of the bclr (instruction 4), which
allows the instruction at the return address (instruction 5) to be executed in cycle 8. The IU2 forwarded the
LR value to the BPU in cycle 9 (which implies that the branch resolution occurs in cycle 10), even though
it is not able to execute from an execution serialization viewpoint until cycle 11.
Without the link stack prediction, the branch would stall on the link register dependency and not execute
until after the LR is forwarded (that is, branch execution would occur in cycle 10), which allows
instruction 5 not to execute until cycle 15 (seven cycles later than it executes with link stack prediction).
3.1.4.2
Position-independent code is used when not all addresses are known at compile time or link time. Because
performance is typically not good, position-independent code should be avoided when possible. The
following example expands on the code sequence, which is described in Section 4.2.4.2, “Conditional
Branch Control” in the Programming Environments for 32-Bit Implementations of the PowerPC
Architecture.
24
Instr.
No.
...
0
1
2
3
4
5
lwzu r30, 4(r1)
lwzu r31, 4(r1)
lwzu r5, 4(r1)
mtlr
bclr
add r3,r3,r20
....
(possible calls to other functions)
....
lwzu
mtlr
bclr
Instruction
Position-Independent Code Example
MPC7450 RISC Microprocessor Family Software Optimization Guide
r4,4(r1)
r4
F1
F1
F1
0
Freescale Semiconductor, Inc.
For More Information On This Product,
F2
F2
F2
F1
F1
1
Table 3-8. Link Stack Example
F2
F2
—
—
D
Go to: www.freescale.com
2
BE
—
—
D
3
I
E0
F1
D
D
D
4
I
E1
E0
F2
5
I
I
E2
E1
E0
—
D
6
E2
E1
—
C
7
I
E2
—
C
E
8
—
—
C
9
10
—
—
MOTOROLA
11
—
E
12
C
C