AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 30

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AN2203

Manufacturer Part Number
AN2203
Description
MPC7450 RISC Microprocessor Family Software Optimization Guide
Manufacturer
Freescale Semiconductor / Motorola
Datasheet

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Issue Queue Considerations
Similar examples could also be given for loads bypassing adds, and multiplies bypassing loads. However,
the ability to use out-of-order instructions is mostly across functional units, and has been extended
somewhat for integer instructions beyond the functionality provided by MPC750 and MPC7400 processors.
3.3.2
The four-entry vector issue queue (VIQ) handles all AltiVec computational instructions. Two instructions
can dispatch to it per cycle, and it can issue two instructions in-order per cycle from its bottom two entries
if reservation stations are available. The primary check is that a reservation station must be available.
Table 3-13 shows two cases where a vector add and a vector multiply-add (vmsummbm) start execution
simultaneously (cycles 2 and 3). Note that the load-vector instructions go to the GIQ because its address
source operands (rA and rB) are GPRs. This example also shows the MPC7450 ability to dispatch three
instructions with vector targets in a cycle (cycles 0 and 1) as well as to retire three instructions with vector
targets (cycle 7).
3.3.3
The two-entry floating-point issue queue (FIQ) can accept one dispatched instruction per cycle, and if an
FPU reservation station is available, it can also issue one instruction from the bottom FIQ entry.
30
Instr.
No.
7
Vector Issue Queue (VIQ)
Floating-Point Issue Queue (FIQ)
vaddshs v20,v24,v25
vmsummbm v10,v11,v12,v13
lvewx v5,r5,r9
vmsummbm v11,v11,v14,v15
vaddshs v21,v26,v27
lvewx v5,r6,r9
Instruction
On the MPC7450, the VIQ can issue to any two vector units, as opposed to
the MPC7400 which only allows pairing between VPU and one other unit.
MPC7450 RISC Microprocessor Family Software Optimization Guide
GIQ5
GIQ4
GIQ3
GIQ2
GIQ1
GIQ0
subf
Instruction
Freescale Semiconductor, Inc.
F2
0
Table 3-12. GIQ Timing Example (continued)
For More Information On This Product,
1
2
1
0
Table 3-13. VIQ Timing Example
Go to: www.freescale.com
2
5
4
3
2
1
D
D
D
0
D
3
6
5
4
2
NOTE
D
D
D
1
I
I
I
4
7
6
2
E0
E0
2
E
I
I
I
5
7
I
E1
E1
E0
E0
E
3
F
E
6
E2
E2
E1
E1
C
F
4
7
E3
E2
E2
5
8
E3
C
C
6
9
C
C
C
10
7
MOTOROLA
11
C

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