AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 27

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

The dispatcher can send three instructions to the various issues queues, with a maximum of three to the GIQ,
two to the VIQ, and one to the FIQ. Thus only two instructions can be dispatched per cycle to the AltiVec
units (VIU1, VIU2, VPU, and VFPU). Only one FPU instruction can be dispatched per cycle, so three fadds
take three cycles to dispatch.
The dispatcher also enforces a rule that only one load/store instruction can dispatch in any given cycle.
The dispatcher can rename as many as four GPRs, three VRs, and two FPRs per cycle, so a three-instruction
dispatch window composed of vaddfp, vaddfp, and lvewx could be dispatched in one cycle.
Note that a load/store update form instruction (for example, lwzu), requires a GPR rename for the update.
This means that an lwzu needs two GPR rename registers and an lfdu needs one FPU rename and one GPR
rename. The possibility that one instruction may need two GPR rename registers means that even though
the MPC7450 has a 16-entry CQ and 16 GPR rename registers, GPR rename registers could run out even
though there is space in the CQ, as when eight lwzu instructions are in the CQ. Eight CQ entries are
available, but because all 16 GPR rename registers are in use, no instruction needing a GPR target can be
dispatched.
The restriction of four GPR rename registers in a dispatch group means that the sequence lwzu, add, add
can be dispatched in one cycle. The instruction pair lwzu, lwzu also uses four GPR rename registers and
passes this rule but is disallowed by the rule that enforces a dispatch of only one load/store per cycle.
3.2.1.1
Table 3-10 contains a code example that shows a dispatch stall due to rename availability.
Instruction 8 stalls in cycle 9 because it needs two rename registers, and 15 rename registers are in use (one
for the divw, and two each for instructions 1 through 7). As only 16 GPR rename registers are allowed,
instruction 8 cannot be dispatched until at least one rename is released.
When the div later completes (cycle 27 in example above), rename registers are released during the
write-back stage and instruction 8 can thus dispatch in cycle 29.
Note that this code uses lwzu instructions, which require two rename registers, only to shorten the contrived
code example. In general, sequences of lwzu instructions should be avoided for performance reasons as they
throttle dispatch to one lwzu instruction per cycle and completion to two lwzu instructions per cycle.
MOTOROLA
Instr.
No.
0
1
2
3
4
5
6
7
8
divw r4,r3,r2
lwzu r22,0x04(r1)
lwzu r23,0x04(r1)
lwzu r24,0x04(r1)
lwzu r25,0x04(r1)
lwzu r26,0x04(r1)
lwzu r27,0x04(r1)
lwzu r28,0x04(r1)
lwzu r29,0x04(r1)
Instruction
Dispatch Stall Due to Rename Availability
MPC7450 RISC Microprocessor Family Software Optimization Guide
Table 3-10. Dispatch Stall Due to Rename Availability
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Freescale Semiconductor, Inc.
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For More Information On This Product,
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